3rdClassLidlToaster

Members
  • Content Count

    9
  • Joined

  • Last visited

About 3rdClassLidlToaster

  • Rank
    Newbie

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hi, I just read the documentation of Xilinx XFFT IP V9.1, read some of the forums threads and also did some testing, but still had some questions especially as far as the IFFT Mode of the IP is concerned. Perhaps somebody did similar experience and can refer to some of them. 1) Is it correct that IFFT mode of IP adds an intrinsic scaling of 1/N to its input which can't be prevented and which is independent from the configuration of the IP and the eventually configured scaling schedule on axi_stream_config bus ? With relation to previous question, is it correct that if i do
  2. Hi, I had two questions concerning Signal generation with Zynq SoC or FPGA. As far as i know there would be four methods to realize a signal generator: Using DDS compiler IP; Using CORDIC IP; Make own implementation in Micorcontroller Part of SoC; Make own implementation in PL Part or FPGA 1) Are these all possibilities for Implementation or i forgot one ? 2) What are the advantages and disadvantages comparing these possibilities ? Greetings
  3. Hi, Yes. It's neither frequency or phase, you have to calculate sqrt(real^2 + imag^2) to get the amplitude and arctan(imag/real) to get the phase. This can be done manually or with ip cores like CORDIC core. If you want the exact values of amplitudes in original signal you have to divide the calculated amplitude by your FFT resolution and multiply it by 2 additionally. Also its important that you choose your FFT resolution accordingly so that you know on which position in the array of complex FFT values you can find the frequency of your interest. That m
  4. Hi i have a question, Is it possible to switch ZMOD DAC 1411 from DC to AC Coupling ? The documentation of LLC IP contains a description of a Port/Input which is called "kCh1CouplinStatic" and "kCh2CouplinStatic" but these are not present in the IP configuration options neither in external nor in internal configuration mode. The Zmod ADC offers these feature but the DAC seems not despite the parameter exists in the documentation. Greetings
  5. Hi i had short question concerned Eclypse Z7 Zmod ADC and DAC and thier Controller IPs and according librarys. Are the functions of the axi zmod library essentially to write to config registers of axi_zmod_ips or can they be written directly with simple functions like xil_out32(baseAddress + registerAddress, value) or a simple pointer to baseAddress of IP on axi bus ? The reason i ask this is, that i build a very basic project with only the ZMOD_DAC_AXI_IP connected to PS with AXI-Lite config port and the ZMOD_DAC_Low_Level_Controller_IP connected to ZMOD_DAC_AXI_IP (without DMA and
  6. Hi, i had the following question. I want to calculate Amplitude and Phase of certain frequencys (frequency domain) from xilinx xfft IP core output (array with complex values). Is it possible to do this with [Rectangular to Polar Translation] Mode of xilinx CORDIC IP core ? If yes, would you prefer this solution over implementing your own FPGA code to calculate amplitude and phase e.g. what would be andvantages and disadvantages ? Greetings
  7. Hello. I had two technical questions about the new Zmod ADC 1410 and DAC 1411 (for Eclypse Z7- and Genesys ZU- Board), which I could not clarify with the help of the data sheets and documentation. 1) What is the maximum signal output and input current ? The ADC 1410 contains the AD9717, which can deliver a maximum output current of 4mA (according to data sheet). But I don't know what influence the additional circuitry has on this value. Additional question here: If the maximum output current is really only 4mA, would it be possible to increase the current to 100mA by an
  8. Hello, I have a question about the Eclypse Z7. While looking at the schematic I noticed that both the VP and the VN pin of the XADC of the Zynq are connected to ground. Does this mean that it is not possible to use it e.g. to read in an external signal with it ? Or is it connected with I/O in another way ? Or could this also be an error in the schematic ? Greetings
  9. Hello, I would have - as already indicated in the title - the following question. I just finished the Zynq book tutorials with a Zybo board. Since this was my first contact with Zynq and Vivado, so to speak, I think I still need some practice before I can start to realize my own projects. Hence the question, how can I proceed further. Are there other books or PDF or video tutorials that are designed in the same way, i.e. a step is explained that can be rebuilt or reprogrammed and the whole project is built step by step from scratch? Is there a kind of road map somewhere