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  1. @zygotCorrect. The answer seems to be NO, and I got it fairly early on in this thread. The powers that be will just need to change their requirement. As it was explained to me it stems from the architect's desire to minimize the number of hard-coded dependencies between all components of a finished product, including hardware and software. Thanks all
  2. Further: Here's an example of a component that adjusts itself at synthesis time. The ZYNQ7 Processing System component adjusts its number of external interrupt inputs at synthesis (or is it validation?) time according to the number of incoming signals (the width of the incoming concat component output bus). When first added and connected the block design shows a mismatch between the input signal and port widths, but this is somehow corrected at synthesis and the block diagram updated with the correct widths. This led me to believe there were perhaps some Verilog accessible net or port attri
  3. Lots to unpack there. Yes, I did look at the links you provided, and it is indeed it is trivial to measure one clock frequency using another known clock. But that's the problem, at component design time there are no "known" clocks. Ok, Your CV has been noted. I wasn't really looking for a discussion, but rather an answer... but since you asked: Hypothetical: I have a component which implements a generic sha3-256 hash function in a 24 stage pipeline generating one hash per clock. The component is implemented as an AXI slave controlled and queried via a register mapped interfac
  4. I am the OP! I think you're missing the point. The component is generic, intended for use in various designs and at various frequencies. I don't care how and who generates the fixed frequency input cock, I just need to know its frequency. Sure, measure it on the fly, but then I'd need a known reference clock to measure it against.
  5. It is a simple requirement. Questioning it doesn't answer the question. The requirement could be based on something as basic as needing to report the operating frequency of a given component to software via a mapped register interface.
  6. Indeed, that is exactly the question, better expressed. Yes, I presently use a module parameter to manually specify the component's input clock frequency. There doesn't seem to be a way to automate this!
  7. I have developed a library component with the usual clock input. The component's logic needs to know at what frequency its clock is running at, which of course is unknown at component creation time. Is there a way, in Verilog, to extract a port or a net's frequency at design synthesis time once the block has been connected to an actual clock? To express the frequency as a wire?
  8. Thanks. That is a long, detailed video... precisely the thing I was hoping to avoid. It's too bad the documentation and support material for the Arty Z7 is so scant and outdated. The project linked at Digilent's Arty Z7 page builds a complete bootable Linux image and would provide a good starting point to add a single IP block, Linux driver, and application. All of the pieces are there except for how to reproduce the critical .bit file.
  9. I've given up on working with the Arty Z7-20 with 20.1 and reverted to Vivado 19.1 and the 19.1 SoCSDK. Using petalinux tools and Petalinux-Arty-Z7-20 project I've been able to create a bootable Linux SD image. So far so good! My objective is to port a project adding AXI slave IP, Linux drivers and applications. The aforementioned project contains a Petalinux-Arty-Z7-20-2017.4-1.bsp file which in turn contains the projects matching Arty_Z7_20_wrapper.bit IP. This project seems like a good starting point for what I need, but where can I find the correct project used to generate Arty_Z7_20_wr
  10. Just what I needed! Any expectation of an officially supported version?