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  1. I've added 50Ohm resistors between each line and the 3.3V rail , and now it works exactly as I expected. Thanks a lot, guys!
  2. I've also tried 60/120 MHz clocks. I've tried to add 50Ohm resistor between lines. I've tried to set pull-up like this: set_property -dict {PACKAGE_PIN V8 IOSTANDARD TMDS_33 PULLUP true} [get_ports {jb_out_p[0]}] set_property -dict {PACKAGE_PIN W8 IOSTANDARD TMDS_33 PULLUP true} [get_ports {jb_out_n[0]}] Unfortunately, all my attempts didn't bring any meaningful results. Maybe someone could provide a working SERDES loopback project?
  3. Hi, my board is Zybo-Z7 20 I am trying to run simple scheme with 2 serdes blocks. I have got 2 switches and 2 leds. I want to run next scheme: 2 switches -> Serializer (2:1) -> ...... TMDS ....... -> Deserializer (1:2) -> 2 leds I've connected PMOD JB1 -> JB2 with 2 wires. But I can't restore a valid signal. I recieve only 11 or 00. (00->00, 01->11, 10->11, 11->11) Serializator settings: Deserializator settings: Scheme: clk_10 =10 MHz clk_20 = 20 Mhz
  4. It seems you are absolutely right. I've double checked it right now. I just forgot to switch the jumper back to QSPI. Now it works again as before. Sorry for the disturbance. Thank you!
  5. Hi, my board Zybo Z7-20 I set LVDS_25 on my PMOD JB pins instead of default LVCMOS33, like tihs: ##Pmod Header JB (Zybo Z7-20 only) set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS_25} [get_ports { jb_out[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1] set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS_25} [get_ports { jb_out[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1] set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVDS_25} [get_ports { jb_in[0] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2] set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVDS_25} [get_ports { jb