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  1. Hi, I am using DDS compiler to generate sin and cos( IQ data) running at 30.72 MHz. I have choosing clock frequency= the input freqeuncy of the DDS= 245.76 MHz, phase width=10 bits, output width=16 bits, phase data=128. When I implement only the DDS and I simulate it, I have no problem. I can see sin and cos wave running at 30.72 MHz(period= 32.56 ns). Please see this figure. In this step, I have no problems, I can generate IQ data running at 30.72 MHz, but when I connect the DDS compiler to Digital Up Converter(wirelless standar LTE=20 MHz, base band sample rate= 30.72 MHz, RF sam
  2. The ZCU111 contains a DAC allowing its to convert directiy to RF, I am thinking to generating a sin cos using DDS compiler running at 30.72 MHz then connecting its to DUP CONVERTER to have the 245.76 MHz then to the IP DAC with interpolation of the DAC; I can reach to result. what do you think?
  3. Hi, please can you give me more detail this approch. How can I do it. thanks
  4. I dont know if I limited for the moment to generate a sin+cos wive runing at 30.72 MHz( base band sample rate of IP DUC is 30.72 MSPS), using this you can have an output until 245.74 MSPS(RF sample rate) then connect its to the DAC with trying to properly configure the DAC. Sorry for my many question, this is my first project that I will do.
  5. Thanks for your explication, you suggest me as a start, i try to limit myself on xilinix IPs ie use IP DDS + IP DUC digital up converter to see these limits. generating a sine + cos using using DDS at 30.72 MHz then connceting its to DUC, I see the result then connect them to DAC and see the reuslts?
  6. Hi, my application is the LTE 4G, the bandwidth is 20 MHz, I am thinking about generating sine and wave(IQ data) at 30.72 MHz then using the IP DUC then the DAC but I am not sure it was be correct or not(for an LTE system at 20 MHz channel bandwidth, the input of this IP correspond to 30.72 MSPS and the output which correpsond to the RF sample rate is ranging to 245,76 MSPS. Using DDS compiler at 30.72 MHz for IQ data then DUP then DAC to have the desired output
  7. Hi, this IP presents the Digital Up Converter (DUC) and Digital Down Converter (DDC), as mentioned in the datsheet, The Xilinx LogiCOREā„¢ IP DUC/DDC Compiler generates Digital Up-Converter modules for a range of output sample rates between 30.76 and 245.76 MHz. These frequencies are far below the desired frequencies
  8. Hi I am using ZCU111 board which support more than 2.6 GHz. My question how to generate a 2.6 GHZ signal using multiple DDS compilers then they will be connected to FFT unitil the DAC. The number of DDS should I use, the configurations of each DDS and etc. I am using vivado hlx. a priori I did not ask the question well. Another thing they is another IP in xilinx The Digital Up Converter (DUC) and Digital Down Converter (DDC). I dont know using this IP can increase the data rate until 2.6 GHZ OF THE SIN AND COS compoents. Sorry for the disturbance
  9. Please another question sir, the IP DDC DUC from xilinx cannot help me to have this task. In datasheet, thanks
  10. I will do my best so that I succeed in my first project. Thanks a lot for your support. Please sir can you explain me more details how can I do this, implementing these parallel DDS, I have problems to understand while I would like to succeed. I am very grateful
  11. just, I would like to explain to you that my goal to generate sines and cosines having a frequency for example 2GHz using DDS compiler. My goal is not generating a 2.6 GHz clock. The DDS cannot generate sin and cos with a frequency higher than the clock freqeuncy. I dont know but maybee, I have confusion between clock frequency and data rate of the sin and cos
  12. Thanks a lot. I am really sorry for the inconvenience . I thinks that I have confused between the rate at which I toggle pins with the rate I can clock logic resources. I thinks that i dont undestand an output of DDS with higher frequency than input. Maybee, I have confused. This is the first example I will. For example using a DDS with a clock frequency 100 MHz. I want to have a sin and cos with higher frequency. Please any help, I am new in FPGA; I dont find any perosn help me. The objective is to have IQ data from DDS compiler with frequency higher than input. Maybee, I should use many DDS
  13. Thanks you for you help. Yes, this is the first design that I do in FPGA. It seems me complex not only FPGA but also telecom, I think
  14. Thanks a lot for your reponse. Please can you give me an idea to increase the frequency of the DDS . The DDS should generate sin and cos. I the amplitude of cos Q is the amplitude of sin. For example , as a start if I want to have an 1GHz in output, How can I do, how can dds compiler, I think I should use many dds but I dont undestand how. or maybee I should use DUC converter but I think that this IP is not able to have higher frequency more than 1 GHz. Thanks a lot sir. I am very grateful if you help me