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  1. thank you sir @zygot for your reply. I even tried to use a .mem or .text file containing hex data it works in the simulation without any problem . Unfortunately, after the synthesis and the generation of the bitstream, I wanted to do the debug to check its operation, a priori it does not read it or it had a problem. I am using ZCU111 ultrascale reg [15:0] ROM [0:4095]; reg [15:0] ROM2 [0:4095]; initial begin $readmemh("I_data.mem", test_memory); $readmemh("Q_data.mem", test_memory); end
  2. hello everyone, i will need help. I would like to know if you have any idea how to store a ROM in fpga from an csv file. I have an CSV file contain hexadecimal data. I want to have a ROM in my design to read data from the external csv file. Thanks
  3. Hello everyone, I am very grateful to you, i always get help through this forum I am implementing a simple example of loopback test in ZCU111 (a signal 2.655 GHz from DAC229_T1_CH0 to ADC225_T1_CH0). It is an external connection using SAM cable. The objective will be that the input of the DAC will be almost equals to the output of the ADC. I am using an ILA which is connected directly to the ADC data stream. The clock of ILA connected to m0_axis_aclk_0. The probes are connected the output data axi stream. I am very grateful if any person can help me. The output of the DAC is quite
  4. @[email protected] Thanks you very much sir for these details. I am very for grateful you. I'm sorry for the inconvenience and my differnt questions. I am a beginner and this is my first project in FPGA. I hope that over time, I will be a good FPGA engineer
  5. Dear sir, I beeg you for a clarification, it can be a stupid question. As i am a beginner in this field but trying to improve myself. I compute an Inverse Fast Fourier Transform of signal generated of DDS compiler. As you know, the inverse Fast Fourier Transform convert data from frequency domain to time domain. Using the dds compiler, in simulation I see sines and cosines in the temporal domain, for that I have doubts on the use of an Inverse Fast Fourier Transform with a signal generated from DDS. I have doubts about this choice given that the dds output is in time domain or Inverse
  6. Hi Colvin, First of all, thank you for your feedback. In fact, I have a confusion between baud rate, clock rate, sampling freqency of a general way of an IP in FPGA. How to know the sampling frequency, clock rate, baud rate (data rate) of an IP. These terms are related to the clock at which the IP is connected. For example if I have an IP cloked at 100MHz, 100 MHz correspond the sampling frequency, the baud rate also correspond to 100Mbit/s or I should know each sample is coded in bits? It can be a stupid question but these terms block me. How to know them of any IP xilinx. Please JColvin,
  7. Hello every body, I have a stupid question. I dont know when any IP is connected to a clock. It sampling freqeuncy correspond to it clock and it baund rate correspond aslo the input clock. example dds compiler clocked at 30 MHz, baud rate is 30Mbit/s and the sampling frequency is 30 Mega hertz. An IFFT also. Thanks for any clarification
  8. @[email protected] Dear sirs, I have a somewhat stipulated question but I cannot understand it. please any clarification in my this example or any example I don't know why the data rate of each IP depends on its clock, the sample rate also depends on the clock. If an IP is cloked at 30 MHz it buad rate is 30Mbit/s if it is cloked to 245MHz baud rate is clocked to 245 Mbit/s. the sampling frequency is dependent on clock
  9. @[email protected] Sir, apologize for my different questions. I started again from the beginning, I clocked my different IPs to the same clock (30 MHz). Configuration of DDS compiler: System clock frequency=30 MHz, phase width=12, phase data= 64. Using this configuration, the dds generates a 0.4675 MHz sine cos Configuration of IFFT target clock frequency=30 MHz, target data throughput=30 MSPS. When I try to compute a small IFFT of (8,16,32) of the generated signal from the dds compiler, the result of computation is correct compared to Matlab. The problem is when I increase t
  10. @[email protected] the sampling frequency should be grater than fmax*2. Or the sampling frequency of fft is 30.72 MHz and my input signal sin cos is 30.72 MHz. I did not think about this criteria. If I want to resolve this problem, I should have a sine cos more the 2*30.72MHz
  11. @[email protected] sorry for all my questions but why you told me that I vialote the nyquist sampling theorem
  12. Thanks sir for you help. I dont undestand very well you question. For me I use IFFT of size 2048 cloked to 30.72 MHz, I choose a pipelined, streaming architecture, I use a scale factor to avoid ovrflow. The other IP is dds compiler cloked at 245.76 MHz generate a sin cos running at 30.72 MHz. I am very grateful
  13. Thanks for you reply sir. In my case, I am using an IFFT of size 2048. I think that a serial to parallel converter with a cdc. The other probelm how can IFFT computes this new data
  14. @[email protected] What do you think sir if I use this IP AXI Clock Converter connects one AXI memory-mapped master to one AXI memory-mapped slave operating in a different clock domain. Thanks.