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  1. Thank you @artvvb I have a following question. In my design, I need to use 1.8V due to a host HW limitation. that's why I am using XADC with 1.8V. Would you please recommend me what pins I should use for 1.8V? Pins in FMC? Are the pins the single ended? Thanks, Tommy
  2. Thanks you for your support. Yes. My board is Nexys Video. One more question, from the reference manual, there is miscellaneous XADC pins. Would you let us know how to use this? Does it support 1.8V? What PACKAGE_PIN should be used for UP and UN. I am seeing errors when I use as like below [DRC NSTD-1] Unspecified I/O Standard: 2 out of 19 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integ
  3. Hi All, I am trying to implement SPI interface and have been using PMOD JXADC. My host board requires 1.8V so I am using SET_VADJ and VADJ_EN for driving 1.8V. With this configuration, it works find with 15MHZ/25MHZ but sometime it doesn't work and from the logic analyzer, I am seeing data skew. Especially pins(spi_reserve1, spi_reserve2) from JXADC bottom row(_N pins), I am seeing the problems. 1. what IOSTANDARD should I use? I am using LVCMOS18. Is that correct or can I use LVDS18? ## XADC Header # 1.8V set_property -dict { PACKAGE_PIN J14 IOSTANDAR
  4. Hi, I have an Vitis application that is using calloc and free frequently. Calloc is working fine just one time and second time it returns NULL Do you have any idea on this? Here is my design information. On Vivado, I am using 64KB local memory when I created microblaze In Vivado - Basys3 - 64KB local memory In Vitis - standalone application, here are two functions. So Set() called first and then Get() called as a pair. 1st pair : Set()->Get() works 2nd pair : Set()-> falied due to cmalloc error - Null returned!!
  5. Thank you. Here is the snapshot of the address editor for my project. Based on your suggestion, code + data should be within 1Mb? 1. data axi_gpio axi_usblite microblaze_local_memory_dlmb microblaze_intc spi_slave vadj_control 2. Code microblaze_local_memeory_ilmb Also, do you know how to set up heap and stack for Vitis application? Does they reside in data segment? Thanks,
  6. If I change address range from Address Editor tab and then validate the design, there is no error and lscripts.ld in Vitis has 1M size range for code. Do you think this method is incorrect? I can't see any size menu during microblaze automation. During automation, I can only select up to 128K this is so small So I used Address Editor tab to change address range. and during validating a design, BRAM size is automatically populated with 1M value.
  7. Hi All, I am trying to increase the size of BRAM since the code segment in Vitis FW got overflowed by 30K I googled the web and found I need to change the Range in Address Editor tab in Vivado. 1. In Address Editor tab, changed Range to 1M for data and 1M for instruction. Save 2. Validate board RTL and worked but I can not increase up to 2M. I am getting error during validating board design. Look like 1M is maximum. Would you please suggest how to increase code segment and data segment more than 1M? Here is the error. ERROR: [IP_Flo
  8. Thank you for your response. I have migrated my RTL design from Basys 3 to Nexys Video and have verified it works well with PMOD JA port but not working at all with JXADC port. All transaction are 0. No data. Do we have any example to use JXADC with VADJ? I am suspecting I need to set SET_VADJ[0] and SET_VADJ[1] with some value and also enable VADJ_EN. Please advice if you have any example to enable JXADC. Thanks, Tommy
  9. Hi After reading an article and answers from the other thread, I have bought the Nexsys Video and am trying to use XJADC for 1.8V. According to Nesys Video reference manual below, I need to program VADJ_EN low and SET_VADJ with 01 and then VADJ_EN high "An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care must be taken to disable the regulator first by bringing “VADJ_EN” low, setting “SET_VADJ(1:0)” and enabling the regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-p
  10. All vhd zip are corrupted in pmod_challenge_r1/r2. What file should I refer to?
  11. Thank you. I forgot to mention my project. I am developing SPI slave through PMOD on 1.8V. Looking at the Nexsys Video, it support VADJ is connected to XJADC. So I am trying to investigate the possible boards with pros and cons. Would you please explain more about "The Vccio for the FMC IO banks can be set in your HDL code using fixed voltage IO pins." So I need to add "set_vadj[0]" and vadj_en in RTL?
  12. @xc6lx45 @zygot Thank you so much for your suggestion I also found Neso - Artix 7 FPGA Development Board. It has a rotary power switch for Bank 35. so look like easy to set up. Do you think it is good option as well? Also I am seeing Nexsys Video. I am not sure how to set up Set_vadj. Do you know how? What is pros and cons to use it? Thank you
  13. @lakshman Hi Lakshman, I am also looking for 1.8V FPGA. Can you please share what FPGA you are using and how to set 1.8V? Thanks and regards, Tommy
  14. Hi, I have Basys 3 for SPI slave and it supports 3.3 PMOD IO but I have 1.8V SPI Master So I need to have a way to use 1.8V PMOD. I went through the forum and found the level shifter at https://store.digilentinc.com/pmod-lvlshft-logic-level-shifter/ but I need bi-directional level shiter. So I am trying to find out the FPGA board can support 1.8V PMOD. Would you please recommend it? Currently I am seeing Nexys Video has SET_VADJ that can support 1.8V. Can someone please confirm it can support 1.8V PMOD IO? If yes then would you please let me know how to program SET_VADJ to 1.8V?