thinkthinkthink
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Posts posted by thinkthinkthink
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We don't have a fix yet but the easiest and most reliable workaround I found was to set the zynq ultrascale QSPI controller in x2 mode from Vivado.
Again, writing the flash and booting from it in x4 mode works fine on the 3EG.
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On 7/5/2023 at 4:33 PM, John J said:
The workaround is to generate an FSBL ELF file with the Xilinx provided files just for programming. This works, but it is another thing to keep track of.
How'd you implement this workaround exactly and are you sure it works ? I'm also using Xilinx files to generate the FSBL elf but after booting from QSPI I still get the error that @Ionut mentioned.
As a side note, QSPI flashing and booting works fine on the Geneys-ZU-3EG.
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You need to clone this repo specifically: ZedBoard-HW. Then you cd into ZedBoard-HW, you checkout the FMC-Pcam-Adapter/master branch and then run the git submodule update --init command and then you can run the checkout.tcl script from inside Vivado v2022.1.
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What errors were you getting when running the checkout script ?
If it's the one I'm thinking of you can just go inside project_info.tcl and replace "avnet.com:zedboard:part0:1.4" with "digilentinc.com:zedboard:part0:1.0" on the line that says "set_property "board_part" $project_obj".
Or make sure you have the board files installed for either of those by going to (inside Vivado) Tools -> Vivado Store....
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Hullo @Tparng,
Just to make sure, are you running our 2022.1 release of this project ? There were a lot of fixes made for this version and it has been tested extensively.
You can find it here: FMC-Pcam-Adapter/2022.1-1 as two archives, one containing the Vivado hardware project and the other containing the Vitis software project.
Alternatively you can recreate it from these sources: Vivado v2022.1 Hardware Project Repo and Vitis v2022.1 Software Project Repo.
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Hullo,
Where'd you get the demo project from and which version of Vivado are you using ?
You can get the latest release for Vivado/Vitis 2022.1 from our github: FMC_Pcam_Adapter Demo Archive.
The Vivado hardware project can be found here: https://github.com/Digilent/ZedBoard-HW/tree/FMC-Pcam-Adapter/master.
And the Vitis software project is here: https://github.com/Digilent/ZedBoard-SW/tree/FMC-Pcam-Adapter/master.
As for the UART interface not working maybe try uninstalling the cypress uart bridge driver and then unplugging and plugging the board back.
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Hi!
We also have a demo project for the Genesys 2 using the FMC-Pcam-Adapter together with 4 Pcams. Here's the link to the Vivado 2022.1 hardware branch and the Vitis 2022.1 embedded software branch.
This example project should work with the Nexys Video too however there are certain changes that need to be made. Firstly, the MIG settings need to be changed to match those in the Nexys Video's Reference Manual and the board constraints also need to be carefully adapted from one board to another one reason being that the Genesys 2 has a kintex7 fpga while your board has an artix7.
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Hi @BMC99
This is how the I2C transactions should look like if you have a system board with an I2C MUX on it (i.e. TCA9548) while wanting to communicate with a Pcam that's also behind another I2C MUX (i.e. TCA9546):
First I'm writing a (1 << 4) to the TCA9548 which is at address 1110000 to open the 5th I2C channel (channel 4), then I'm writing a (1<<0) to the TCA9546 which is at address 1110001 to open its 1st channel (channel 0) and only then can I write to or read from the registers of the OV5640 which is at address 0111100. In our current published projects involving the FMC-Pcam-Adapter we don't open all channels at once. According to the TCA9546 datasheet, when a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus so make sure you do that as well.
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It's in our vivado-library repo.
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My bad, I was looking at the bits after the start/repeated start condition.
Also are you using an AXI IIC IP or the PS_IIC inside the zynq to communicate over i2c with the i2c mux on the fmc pcam adapter ?
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I only see you writing 11000000 (0xC0) for addressing the TCA9546A i2c slave when you should be writing 11100000 (0xE0).
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There's more on that Eclypse-Z7/Releases page. You should look for the release with the v0.3 tag. There's where you'll find the debian image you're looking for.
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You have to run the digilent_vivado_checkout.tcl script from inside the digilent-vivado-scripts submodule.
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Hullo,
Also make sure the ribbon cable is connected correctly both on the Pcam and in the MIPI connector on the Zybo.
Here's a few screenshots on how to do it properly from the Zybo's Reference Manual.
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Hi!
What version of Vivado are you using ?
Here's the hardware (Vivado 2022.1) branch: Zybo-Z7-20 Pcam-5C Vivado 2022.1 project.
And here's the software (Vitis 2022.1) branch: Zybo-Z7-20 Pcam-5C Vitis 2022.1 project.
They have been tested recently and are working correctly.
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In the design_1_wrapper.vhd file under Entity in the Port declaration section.
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Quote
## Buttons
set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
I know it might be a little misleading but your GPIO input port is not called "btn" but "btn_tri_i" so your constraints should be: btn_tri_i[0] and btn_tri_i[1].
Open the wrapper file by double clicking on it and you'll see that your design has no ports named "btn". When manually constraining ports you should always check the ports declared under Entity inside the wrapper file to get the complete port name.
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How does your .xdc constraints file look like ?
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17 minutes ago, poiuyt said:
Thank you for your quick response ! Is there an ACK bit between the two bytes ?
Absolutely. The sequence should look something like this: Start -> Pcam address 7bits + Write bit -> ACK -> Register Addr High 8 bits -> ACK -> Register Addr Low 8 bits -> ACK -> Write Data 8 bits -> ACK -> Stop.
The above sequence is meant for a Write transaction. For Read transactions you have to first WRITE the register address and then re-address the Pcam but this time ending in Read bit like so:
Start -> Pcam address 7bits + Write bit -> ACK -> Register Addr High 8 bits -> ACK -> Register Addr Low 8 bits -> ACK -> Repeated Start -> Pcam address 7bits + Read bit -> ACK -> Read Data 8 bits -> NACK -> Stop.
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It's pretty simple, first you address the Pcam itself (7 bits) and then you send the register address as two bytes of data over I2C, the most significant 8 bits of the register address followed by the least significant 8 bits.
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They should appear if you click on the Refresh button in the bottom left corner of the page. After they show up you'll also need to click on the install icon/button that's in the Status column to the left of the Vendor column.
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We have this guide called Installing Vivado, Vitis, and Digilent Board Files that shows you how to add board files manually. For 2021.2 you should click on the Appendix: Installing the Board Files via the "vivado-boards" Github Repository drop down and follow the steps. It basically tells you to download the board files from our github and make a TCL script that automatically tells Vivado where to look for boards whenever you open a new instance of Vivado.
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Also you need a post-implementation bitstream for the project to work on the board. So show us the Message tab and the Implementation log to see why vivado couldn't implement your design. The Synthesis log you uploaded wasn't enough.
Genesys ZU-5EV Setting VADJ to 1.8V
in FPGA
Posted · Edited by thinkthinkthink
You can force a certain VADJ level with xlconstant or gpio IPs in your block design. Check out the 5ev/oob/master branch of our Genesys ZU repo that contains the board's out-of-the-box demo.
Also, take a look at the XDC file of that OOB project, more specifically lines 227 through 237.