thinkthinkthink

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  1. I'd recommend starting with Vivado and Vitis 2020.1 or 2021.1.
  2. I'm still not familiar with all the intricacies of the PS, but you're getting your clocks from it so make sure the PS isn't in some idle state where everything is stopped including the PLLs, maybe put a while(1) loop at the end of your code. The PLLs inside the PS should still give out clock signals even if the ARM cores are in a parked state where they do nothing but dunno what's stopping them. Also try giving the ZYNQ 7000's technical reference manual a read too, it's called UG585 Zynq 7000 TRM, you might find something.
  3. You don't need the GPIO IP, get rid of it, you just need to constrain the CTRL external input port to a switch or button in the board XDC file. It's probably because you connected the GPIO IP inputs/outputs to the switches that your CTRL port does nothing.
  4. Disconnect from the Board flow tab and try again with manual constraints. Maybe it's also worth deleting the uartlite IP and adding it back again.
  5. You can also try regenerating the bitstream after clearing IP cache from Tools->Settings->IP and/or manually constraining those pins in the board XDC file to your UART interface. It's pretty pointless to do any debugging if those pin connections haven't been made inside the FPGA. What I hope will happen is after you add an ILA to your design and regenerate the bitstream, Vivado will finally do its job properly during the synthesis and implementation phases.
  6. Check your UART interface with an ILA. This should be the first thing to do when debugging in Vivado.
  7. Nah, it's correct what you did with the external port and XDC file and it should have worked, maybe put an ILA on that line and see if it toggles correctly or try other switches maybe even the buttons. It could be that the switch is defective in which case maybe try cleaning it with some isopropylic alcohol.
  8. Maybe you should try the new low-level IP that was made for the Zmod ADC/Scope: Zmod Scope Controller.
  9. You're also limited by the processor to peripheral interconnect but then again you can just add another interconnect IP in your block design.
  10. For the PS side you can use 2 XGpiops outputs and 1 Xgpiops input while on the PL side you'll have to either write your own VHDL/Verilog module that adds the 2 integers and outputs the sum into the Xgpiops input of the ZYNQ processing system or check if Xilinx offers IPs that perform additions/subtractions etc that come with your version of Vivado.
  11. Have you followed this guide: Installing Vivado, Xilinx SDK and Digilent Board Files ? At the end there's a drop-down Appendix that will tell you of another method to use those board files you got from our github, you basically create a TCL script that will be run by Vivado at startup everytime.
  12. If you go to Releases in the root repo for the Genesys ZU you'll find two SD card images for each board variant but it also tells you that: "Use a suitable imager tool to write the image file to the SD card. On Windows we recommend SDImager, an open-source tool. On Linux use the "dd" tool. Extract the *.img file from the archive and load it with the imager tool. Keep in mind that this will overwrite ALL data on the SD card.". Personally, I think Rufus would work too on windows in this case but I haven't tried. Hope this helps.
  13. In the Board Flow tab right-click on the connector that's assigned to your Pmod's output and select Disconnect Board Component. Then right-click the output port of the Pmod and select Make External (or select the port and press Ctrl+T to make it external). You can get the XDC file for the Zybo Z7-10 from here, add it to your project and uncomment the lines corresponding to the JA Pmod Header. Now replace the name of the ports with the name of your Pmod output interface, it should look something like this: If you want to know how I knew the exact names of the Pmod_out interf
  14. Yeah... about that... I've also tried a bunch of things but couldn't get c++ code to run on microblaze either. Not even a simple cout would work. Even on zynq processors that have ARM cores you have to be careful with c++.
  15. Which board are you running that on, Zedboard or Genesys 2 ? Did you just copy and paste the code from the Genesys 2 vitis project to your Zedboard vitis workspace ? The Zed project uses the PS_IIC i2c controller that's inside the ZYNQ processing system while the Genesys 2 one uses an AXI_IIC IP with SCL frequency set to 400kHz. There's a lot of driver differences between the two i2c controllers. Why your processor is stuck on that line of code is because you're either not getting an ACK from your i2c slave and you're not getting a NACK either somehow, or maybe because the i2c bus