thinkthinkthink

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  1. The default installation of Vivado 2020.2 should have come with Vitis 2020.2 as well. Anyway, you're supposed to clone the Software repo for your board and then checkout the HDMI/next branch. For some reason there's no workspace folder called ws in this repo branch but you can just create it yourself. Launch Vitis and use the ws directory as your workspace. You can just close the Welcome page that Vitis opens with empty workspace directories. Then go to Xilinx -> XSCT Console and this will open a console on the bottom right side of Vitis. In that con
  2. There was no official support from Xilinx for Vitis AI on ZYNQ-7000 devices last year, only for UltraScale+ specifically ZCU102/104 boards and Alveo cards but one of our interns managed to make it work in some limited capacity on the Zybo. Hopefully things have changed since then but I haven't been following Xilinx on this matter so I wouldn't know. But I'll ask around and see if the AI branches should go public or if they were only meant for internal use.
  3. I think I've told you that you can daisy chain both PmodHYGRO and PmodAQS without needing to use both rows on the pmod port of your board. It would look something like this: (Please don't mind my horrible paint skills.) And because they have different i2c addresses there would be no conflict when trying to communicate with any of them while they're connected like this. Their Pmod_out interfaces don't have to be connected together inside the block design because they're going to be physically connected by way of daisy chain, just be careful when you're writing the xdc
  4. I honestly think you don't need to have the PmodHYGRO and PmodAQS IPs present in the block design anymore since you'll do all the work with the AXI IIC IP so they can be removed. What you have to pay attention to though is at the way you're gonna connect them to the Pmod port on your board and that's where the xdc file comes in. Make sure everything is correct by also checking the schematics of your Zybo (specifically the first page where it shows the Pmod ports) and your PmodHYGRO and PmodAQS. Also, at first try to learn and get experience by working with the 2 pmods on two differen
  5. The PmodTPH2 and some female to female cables should probably do the trick but make sure PmodHYGRO and PmodAQS have different i2c addresses. Edit: Actually from what I can see you can daisy chain the PmodHYGRO and the PmodAQS by connecting one into the other without needing additional connectors/cables since their SDA and SCL pinout match perfectly.
  6. Actually, now that I think about it the PmodIOXP isn't right for your application since both the PmodHYGRO and the PmodAQS have to communicate with the processing system via the I2C protocol. The outputs of the PmodIOXP are all GPIOs which mean you'd have to get into bit banging territory to obtain proper I2C communication with the other 2 Pmods and this will add more complexity to your project but it should be a fun challenge. What I mean by "constraining their input/output interface to a Pmod port of your choice on your board" is adding this xdc constraints file into your project and un
  7. The PmodIOXP doesn't necessarily need it's own IP since you can just use one of Xilinx's AXI IIC IP or the IIC inside the ZYNQ processing system by constraining their input/output interface to a Pmod port of your choice on your board according to this pinout (which you can easily find on its Resource Center page): And at the bottom of the Resource Center page you can even find a link to a demo project done by Analog Devices. But the most important part is to get familiar with the ADP5589 which is the main component of the PmodIOXP by checking out our Reference Manual and its dat
  8. I don't think the AI branches are public right now.
  9. Dunno what to say. Have you tried opening the SDK standalone, make a new folder and use it as workspace for the SDK and then go to File > New > Other > Xilinx > Hardware Platform Specification and look for the hdf file you exported from Vivado. This should create a new hardware platform which you can use to create an application project. Also make sure you don't have spaces in the paths of your Vivado projects and SDK workspaces, and keep path lengths to a minimum.
  10. Those critical warnings are of the "can be ignored" type and won't cause you any trouble but just to make sure, you were able to properly generate a bitstream correct ?
  11. Sure, you can ignore those critical warnings since they'll just be overwritten by the board configuration files. Those red errors you're getting shouldn't be there, I thought vivado 2020.2 should have fixed those wrapper file doesn't get updated after you've made some changes to the block design/constraints file bug, but you could get rid of them and make it work. Also, I hope you're not messing with the design_1_PmodBT2_0_0_board.xdc file as it should be read-only. Please let me know if you've got it working properly, I feel like I'm doing a terrible job at explaining but I re
  12. Sorry I might have messed the order on those pins since jd_pin2_io should be on PACKAGE_PIN W7 and not jd_pin1_io. That's why you're getting all those critical errors. But if you're working with board flow then you don't actually need to constrain any ports.
  13. If you look in the wrapper file you should see these jd_pin*_io ports inside the entity. Now these are what you should add inside the contraints xdc file. First go to our github here: Zedboard-Master_xdc and copy what's inside that file or download it and add it to your constraints. Then look for the JD Pmod constraints that should start at line 124, uncomment them and replace what's inside the squiggly braces. Finally, your JD contraints should look something like this: Unfortunately I don't have a PmodBT2 on me to test this out but do let me know if it works or if yo
  14. Hmm, there do seem to be misleading photos in that tutorial but that shouldn't pose a problem if you've followed the first few steps. When creating a New Application Project for the ZedBoard and you have a ZYNQ processor in your block design the target processor should be called something like ps7_cortexa9_0.
  15. What version of Vivado have you tried this on ? Because on 2020.1 ui_clk is 100MHz by default. However you can try playing around with the MIG's internal settings to try and obtain an ui_clk of 100MHz. Double click on the MIG and then keep pressing Next until you see this: Make sure Clock Period is set to 2500 ps, this should be the default setting that can give you an ui_clk of 100MHz.