# JonK

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@zygot Thanks for your discussion. If and when you feel like it, have a look at my broader question posted here. In it, I also include my motivations: To learn how it can be done and if it can be done, as I may need to know how to do this someday and I'd like to get it out of the way now as a matter of educating myself using this highly simplified conceptual idea; and, To learn how well the compiler optimizations work, by comparing the brute-force method I already know how to implement against an algorithm that self-optimizes and doesn't depend on later analysis by the compile

@zygot Either I misunderstand your pointing finger's direction or else that's not the answer I'm looking for. I know I can pass in a parameterization. That's not the problem. The problem in my mind is the tree structure implied by the parameter. For N <= 3, there's no need for any instances of a dabble (if.) But I need N-3 of them for 4 <= N <= 6, need (N-6)*2+3 of them for 7 <= N <= 9, and need (N-9)*3+9 of them for 10 <= N <= 12, (N-12)*4+18 for 13 <= N <= 15, (N-15)*5+30 for16 <= N <= 18, etc. Worse, the tree depth continues to vary and the wiring assig
3. ## General N-bit binary to M-bit BCD output module in verilog

My modest background has been with VHDL, but it dates back to the early 2000's and I've been away from any HDL for more than 15 years. My last project was a few self-tutorials on the Xilinx 4000 series part, to date myself a bit. (I enjoyed the language experiences but hated the crappy floor planning tool and so floor-planned out everything by hand, instead, with far far better success that way.) I also have only just started at this forum site and have only read a small number of posts here. I hope the following is sufficiently clear. If not, I'll try to improve it based upon comments I

One more noteworthy event, today. Someone on the Xilinx forum finally responded with a useful suggestion: a link to the full download of 2020.1!! Using that, plus WGET, I was able to fetch the file onto my machine -- along with the "update 1" file, too. I haven't yet unbundled the .tar.gz files, yet. But I will and I fully expect the installation to work out okay. The files downloaded without more than a few small problems (SSL decryption issues plus one event where the download simply stalled for 15 minutes after which I just canceled and then re-started it without much further problems.)

Just a final note, I suppose, to cap this off. I have had very good success using 2017.4 (with its added update-1) with the Basys 3 board I just received. Everything compiles, downloads, tests out, and I can save it in the SPI memory, as well (which isn't the same as the one mentioned in the video.) Everything just works good. So I'm in high cotton. I am still not happy with Xilinx. They aren't a partner I'd want. They are a partner I may wish upon my competition. But there are some nice folks here. Zygot inspired me and kept my spirits up and also pointed me in various dir

Thanks, Tim. (And Zygot's response to you was also appreciated.) I'm weird. I perform full backups of all my drives every single day. These backups are daily-rolling (so I have 7 of the most recent days), one of which is rolled over to a weekly-rolling group where I keep another 7 of the most recent once-a-week snapshots), one of which of these is rolled over into a 7-week-rolling group where I also keep a 7-entry rolling group. As a part of that process, I also perform a check disk operation, just prior, and save the event logs. These operations are combined into an automated process tha

Thanks. That makes me feel more comfortable. I've been working on downloading 2018.3 ever since posting above and have had no luck despite it being about the same size download as 2017.4. So it's good to hear that I won't need it as it's being a serious pain. I'll get started testing out the drivers to see if the board is recognized now. Hopefully, it will be. I've held short of plugging it into the computer (installer warned me not to do so until it was finished.) So it's time to find out. Thanks, Jon

Oh, it definitely lists the XC7A35T. In fact, several. They just don't appear to be exactly the part on the Basys 3. I notice differences in the exact numbers show on Digilent's site and the list that 2017.4 presents to me when I'm selecting a device.

Okay. It doesn't support the XC7A35T-1CPG236C. It has an "E" and an "I" part type, but not got the needed part, apparently. The LUTs don't match up with any of the listed parts, either. (At least I was successful with 2017.4, update 1.) I'll now see about 2018.3. I've some hope about it. The size isn't that much larger than 2017.4 and the installer uses a similar splash screen. And I believe I found forum discussions of the XC7A35T-1CPG236C dated about August or September of 2017. So perhaps that means 2018.3 will have it listed. I can hope.

In addition to the Xilinx Unified Installer 2020.1, I've tried the Xilinx Unified Installer 2019.2 and got the same terrible results. I then decided to go all the way back to the Xilinx Unified Installer 2017.4, skipping over 2018.3, and the download process almost looked like it would work better. Two things were different, this time. The first is that I received a popup regarding allowing Java to go to public systems via the Microsoft Defender barrier. (I had received a similar message the first time I tried using the 2020.1 installer, too, but that only happened just the once for it. S

I used to teach at Portland State University as an adjunct professor, in the 1990's. I'm old enough now that I can go take community college credit courses (or non-credit) for free, assuming paying students don't already fill the classes. And I'd be formally enrolled. (I took the entrance tests two years ago and scored a perfect score on their two primary topics: math up through calculus and English grammar. So I'm sure I qualify for their classes, already.) Digilent does offer some impressive discounts for students. And I don't mind making the lives of community college teachers a living hell