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Niță Eduard

Digilent Staff
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    Niță Eduard got a reaction from drkome in My Risc-v Processor Running in Operation Does not Work in FPGA.   
    Hi @drkome,
    Thank you for your screenshots and answers.
    Since you are implementing a pipelined design, you should make sure that there are no hazards.
    Are you dealing with hazards? If not, you should choose how you fix hazards (stalling instructions or dedicated hardware). I don't think venus detects data hazards, so in your case you will need to add bubbles (noop instructions) to stall.

    Take a look at this presentation:
    https://inst.eecs.berkeley.edu/~cs61c/su20/pdfs/lectures/lec14.pdf
    Study the Data Hazards and Control Hazards sections.

    Here is how to add an ILA to your design. You should use this to visualize your signals inside the FPGA:
    http://web.mit.edu/6.111/www/f2017/handouts/labs/ila.html

    Also, how are you writing data from the register file to the LED pin? If you just connect bit(0) from the ALU Result it probably won't work, because you will change your instruction. You should verify that you are writing data at address 3 and if so, write the value to a flip flop that is connected to the LED.
  2. Like
    Niță Eduard got a reaction from rspanbauer in MATLAB integration with Analog Discovery   
    Hi @rspanbauer,
    By what you're describing, it looks like you're using the old toolbox (made by Mathworks):
    https://www.mathworks.com/matlabcentral/fileexchange/40344-data-acquisition-toolbox-support-package-for-digilent-analog-discovery-hardware?s_tid=FX_rc2_behav
    Instead of the new toolbox (made by Digilent):
    https://www.mathworks.com/matlabcentral/fileexchange/122817-digilent-toolbox
     
    Check out this Getting started guide:
    https://digilent.com/reference/test-and-measurement/guides/matlab-getting-started
  3. Like
    Niță Eduard got a reaction from JColvin in I want Pmod Driver files Zynq Soc Peripheral Drives files and programming files of the Avnet Zedboard 7000 without which I cannot do the DAC or ADC interfacing with Zedboard please help me some body with this issue   
    Hi @Goubinda Sarkar,
    You can find the code from the Analog Devices repository on an older branch
    https://github.com/analogdevicesinc/no-OS/tree/2018_R1/Pmods/PmodAD4
  4. Like
    Niță Eduard reacted to pikeaero in Running WaveForms on PinePhone   
    I am running WaveForms on my Linux (ARM 64-bit) PinePhone (with the optional Keyboard Case and docking bar), and I absolutely love it!  The PinePhone is perfect for 90% of the use cases where I use the AnalogDIscovery2. It makes the whole thing much more portable and bench-top friendly.
    I couple things I would ask the WaveForms group to consider;
    A) Better touch gesture handling. (I use a tiny Bluetooth mouse right now, without that, it's painful to use WaveForms with touch-only).
    B) A way to collapse/shrink the real estate at the top to make more useful pixel space for the traces.
    C) Make a 'pacman' package for Manjarno Linux and the like. I installed on Manjarno Linux from the Debian package by coloring outside the lines  a little bit. It runs great, very responsive, no issues so far other that what I've mentioned above!
    I love this setup very much!
    Thanks for the great tools!





  5. Like
    Niță Eduard got a reaction from dddddddq in Question when using vivado sdk to call IP generated by HLS   
    Hi @dddddddq,
    See this recommend flow for working with AXI4-Lite interfaces from the Vivado HLS user guide (p 109).
    https://docs.xilinx.com/v/u/2018.3-English/ug902-vivado-high-level-synthesis
    According to this, you will need to use XMylenet_Get_out_V in order to retrieve the prediction. Maybe this is why subsequent calls are not working?

  6. Like
    Niță Eduard got a reaction from filipj in HLS Embedded Vision Workshop error; hls_video.h not found   
    Hi @filipj,
    Good catch on the AXIS port difference
    It seems to be a bug in 2020.1 where it does not get synthesized correctly:
    https://github.com/Xilinx/Vitis_Libraries/issues/28
    Try to use the xf_infra.hpp file from the 2020.2 version of the library and let me know if that fixes the HLS synthesis
    https://github.com/Xilinx/Vitis_Libraries/blob/2020.2/vision/L1/include/common/xf_infra.hpp

    Thanks,
    Eduard
  7. Like
    Niță Eduard got a reaction from altunkenan in Zybo Z7-20 hmdi input outpu demo   
    Hello @altunkenan,
    Regarding the jumpers, you should set the JP6 jumper(highlighted in green) to WALL instead of USB, since you're powering the board externally.
    You should also set the JP5 jumper(highlighted in red) to change the programming mode to JTAG, just to be sure.


  8. Like
    Niță Eduard got a reaction from Kyle_ISL in Removing debug logic of pcam-5c reference design   
    Hello @Kyle_ISL,
    Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format.
    For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here:
    https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf
    https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf
    https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf
    Best wishes,
    Eduard
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