Niță Eduard

Digilent Staff
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  1. Like
    Niță Eduard got a reaction from Guru Tim in Memory read error at 0xF8F00208. Cannot halt processor core, timeout.   
    Hello,
    Sorry for the delayed answer.
    I have managed to replicate the error using the same hardware setup as described, and it is thrown when I try to program the board while JP5 is set on QSPI. Can you try moving the jumper from QSPI to JTAG, as in the photo, and then program the board again? For me this fixed the issue.

    Best wishes,
    Eduard

  2. Like
    Niță Eduard got a reaction from GENIECUBE in Memory read error at 0xF8F00208. Cannot halt processor core, timeout.   
    Hello,
    Sorry for the delayed answer.
    I have managed to replicate the error using the same hardware setup as described, and it is thrown when I try to program the board while JP5 is set on QSPI. Can you try moving the jumper from QSPI to JTAG, as in the photo, and then program the board again? For me this fixed the issue.

    Best wishes,
    Eduard

  3. Like
    Niță Eduard got a reaction from fpga_123 in Driving the PMOD SSD from Xilinx SDK   
    Hello,
    Your idea is indeed correct, alternating between the displays really fast gives the illusion that both are turned on at the same time.
    As of implementing it, you could do something similar to this pseudocode
    selection <- read selection bit while(program runs){ data0 <- aquire digit value for display 0 data1 <- aquire digit value for display 1 display0 <- translateData(data0) // translate data0 into a seven segment encoding display1 <- translateData(data1) // translate data1 into a seven segment encoding if(selection == 0) then write display0 to data bits of the SSD else write display1 to data bits of the SSD selection <- negated(selection) }
    Best wishes,
    Eduard
     
  4. Like
    Niță Eduard got a reaction from Kyle_ISL in Removing debug logic of pcam-5c reference design   
    Hello @Kyle_ISL,
    Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format.
    For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here:
    https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf
    https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf
    https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf
    Best wishes,
    Eduard
  5. Like
    Niță Eduard got a reaction from iyer25 in Zybo Z7-20 - xfopencv: hls::stream is read while empty   
    Hello @[email protected],
    Have you modified the hls_helper file found on github? In your screenshot I see that the errors occurs at different lines when compared to the github source file.
    Have you perhaps changed the inR, inG, inB from xf::Mat to ap_uint<8>?
     
     
  6. Like
    Niță Eduard got a reaction from Han_newbie in Unable to dowload Digilent Plugin for Xilinx Tools   
    The link will redirect you to this website
    https://mautic.digilentinc.com/adept-system-download
    Fill in the form and the download should start automatically.
  7. Like
    Niță Eduard got a reaction from Han_newbie in Unable to dowload Digilent Plugin for Xilinx Tools   
    Strange, I seem to be able to download it
    I have attached the zip file from the download section
     
    libCseDigilent_2.5.2-x86-x64-Windows.zip