Niță Eduard

Hello @Moeen, Unfortunately I do not have a Nexys Video at hand to test the demo, but you should try taking a look at this post: The demos are similar, so what is written there can be applied here as well, mainly try starting the demo with both cables plugged and check the HPD signal. Also check if the TX test pattern works. I'm not sure if the upgrade screwed to 2018.3 screwed anything, but if it still doesn't work try the demo in 2018.2.

Hello @altunkenan, Regarding the jumpers, you should set the JP6 jumper(highlighted in green) to WALL instead of USB, since you're powering the board externally. You should also set the JP5 jumper(highlighted in red) to change the programming mode to JTAG, just to be sure.

Hello @Moeen, According to the readme on github, you should use a baudrate of 115200 instead of 9600. Perhaps this will fix the issue. Best regards, Eduard

Basically, if you want to make changes to what was auto-generated based on the xsa/hdf, you can do so by modifying system-user.dtsi. So you don't have to always modify it, only when you want to change something.

Hello @thoonky, I don't think the 2017.4 version of the demo is compatible with Petalinux 2021.2. If you want to use the 2017.4 demo, you should use Petalinux 2017.4. We have an upgraded version of the project for Petalinux 2021.1, which can be found here https://github.com/Digilent/Cora-Z7-OS/tree/07S/Petalinux/upgrade , on the upgrade branch. I have also attached a bsp file of the 2021.1 project. Best wishes, Eduard cora-z7-07.bsp

Hello @Antonio Fasano, Can you try to make the following edits on your makefile? https://support.xilinx.com/s/article/75527?language=en_US I remember having these issues when moving from SDK to Vitis 2020.1. However, when moving from Vitis 2020.1 to Vitis 2021.1, we also encountered makefile issues, and these were fixed by making the following change (in addition to the ones from SDK->Vitis): https://github.com/Digilent/vivado-library/commit/0390827da381069bf0c0a7f46584bcaaadc3ca01#diff-bb9af5d1915da1fbc132ced081325efcd2e63e4804f96890f42e9739677237a4 Hope you find these changes useful. Best wishes, Eduard

Usually undefined reference to main occurs when the main() function does not exist in the program. Can you verify that you have a main() function in your code? If you do have a main() function in your files, can you post your source files?

Hello @rmccormack1, What version of Vitis are you using? Also, besides the makefile error are there any other errors in the console? Can you provide the messages from the build console? Best wishes, Eduard

Hello @miezekatzen_dompteur, In the beginning of that tutorial it is stated that a license for the TEMAC IP is required. Have you followed this guide on how to obtain a license for it? https://reference.digilentinc.com/vivado/temac Best wishes, Eduard

Hello @lukelouyu, Do you use an external power supply? I have found these forum posts with a similar issue which were fixed by a) switching the micro-USB cable b) changing the power supply Best wishes, Eduard

Hello, Can you post the source of your UART implementation? Also, does your implementation use any parity bits? In my case, using a parity bit made the terminal also display garbage. Best wishes, Eduard

Hello, Sorry for the late reply. Perhaps using a pipeline directive to write the data in burst mode may fix the issue. Take a look at these code snippets. I'm not sure how HLS will handle the switch statement, but from the page linked above it states that: So an issue may also be caused by this. Maybe try to only send the data without the switch statement and see if the constants are sent correctly. Best wishes, Eduard

Hello @Kyle_ISL, Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format. For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here: https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf Best wishes, Eduard

Hello @Marycruz, Firstly, I have also encountered the vivado launcher error from time to time. It is nothing serious and can be ignored. Secondly, Vivado and the SDK can have problems if the paths to the project contain whitespaces https://www.centennialsoftwaresolutions.com/post/xilinx-sdk-internal-error-the-folder-c-metadata-is-read-only I would recommend extracting the project in a folder that does not contain whitespace such as "Marycruz_Blas_Hder" or something equivalent. Best wishes, Eduard

Hello @HOOKJANDRO, hls_video.h is not found because in Vitis HLS 2020.1 it has been deprecated and replaced with Vitis Vision Library, as says here: https://www.xilinx.com/support/answers/75345.html Another major change in Vitis HLS 2020.1, is that it no longer provides compiled OpenCV libraries. This means that you will have to compile the libraries yourself if you want to use testbenches. The workshop is not compatible with Vitis HLS 2020.1, but I have attached source files for a Sobel Edge Detection in Vitis HLS below (in the Vitis Vision library the Sobel algorithm generates both X and Y gradients). I recommend that you read this post https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Using-Vitis-Vision-Libraries-and-OpenCV/td-p/1170435 since it details the process of setting up a Vitis HLS project. If you have any more questions feel free to ask. Have a nice day, Eduard edge_detection.cpp edge_detection.h edge_detection_test.cpp