Niță Eduard

Digilent Staff
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Everything posted by Niță Eduard

  1. Hello @Antonio Fasano, Can you try to make the following edits on your makefile? https://support.xilinx.com/s/article/75527?language=en_US I remember having these issues when moving from SDK to Vitis 2020.1. However, when moving from Vitis 2020.1 to Vitis 2021.1, we also encountered makefile issues, and these were fixed by making the following change (in addition to the ones from SDK->Vitis): https://github.com/Digilent/vivado-library/commit/0390827da381069bf0c0a7f46584bcaaadc3ca01#diff-bb9af5d1915da1fbc132ced081325efcd2e63e4804f96890f42e9739677237a4 Hope you find these changes
  2. Usually undefined reference to main occurs when the main() function does not exist in the program. Can you verify that you have a main() function in your code? If you do have a main() function in your files, can you post your source files?
  3. Hello @rmccormack1, What version of Vitis are you using? Also, besides the makefile error are there any other errors in the console? Can you provide the messages from the build console? Best wishes, Eduard
  4. Hello @miezekatzen_dompteur, In the beginning of that tutorial it is stated that a license for the TEMAC IP is required. Have you followed this guide on how to obtain a license for it? https://reference.digilentinc.com/vivado/temac Best wishes, Eduard
  5. Hello @lukelouyu, Do you use an external power supply? I have found these forum posts with a similar issue which were fixed by a) switching the micro-USB cable b) changing the power supply Best wishes, Eduard
  6. Hello, Can you post the source of your UART implementation? Also, does your implementation use any parity bits? In my case, using a parity bit made the terminal also display garbage. Best wishes, Eduard
  7. Hello, Sorry for the late reply. Perhaps using a pipeline directive to write the data in burst mode may fix the issue. Take a look at these code snippets. I'm not sure how HLS will handle the switch statement, but from the page linked above it states that: So an issue may also be caused by this. Maybe try to only send the data without the switch statement and see if the constants are sent correctly. Best wishes, Eduard
  8. Hello @Muhammed Kawser Ahmed, We currently do not have an example for software image processing for the Pcam project. This HDMI Input/Output project does software processing, which could be used as a starting point, if you need software image processing. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start However, edge detection would be slow if implemented using the processor. We also have the Embedded Vision Workshop, which guides you to create a demo which takes Pcam image data as input, processes it using a Sobel Edge Detection IP (whi
  9. Hello @Engr_Shan, We have several example projects which use the XADC IP. I'm not sure what board you have, but you if you want an HDL-only project, you can look at the following: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-xadc-demo/start where the LED associated with a channel brightens as that channel's voltage increases https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-xadc/start where the 7-segment displays show the voltage difference If you want to use it with a Zynq processor, you can check out this demo: https://refer
  10. Hello @seaover, The error you are encountering is very similar to the one described in this post on the Xilinx forum . Can you try to modify your makefile according to the process described in that thread? Also, take a look at this answer record, which is related to that post. Best regards, Eduard
  11. Hello @Zakir Hussain, These warnings appear in versions of Vivado greater than 2017.4. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted.  You can ignore these warning, since for Zynq based designs they won't cause any issues. For more information regarding the warning, please see this section of the reference manual. Best wishes, Eduard
  12. Hello @rt54321, You can use the commands mrd and mwr in the XSCT (Xilinx Software Command line Tool) to read/write values from/to registers. You can find the documentation for these here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1208-xsct-reference-guide.pdf Although not related to the project, here is a tutorial which debugs a VDMA IP using XSCT commands on registers: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-25-Debugging-issues-on-the-AXI-VDMA-IP/ba-p/941372 You could try clearing the interrupt pending register, which
  13. Hello @rt54321, From what I can tell, you implemented the button connection using the "Connect board component" option. This forces the AXI GPIO to be configured as "All inputs". I would recommend disconnecting the AXI GPIO from the board sidebar, reconfiguring the AXI GPIO to allow both inputs & outputs and then making the port of the AXI GPIO external (and after that creating an .XDC and constraining your ports). The XDC would look similar to this (Disclaimer: I have used a ZYBO Z7 to constrain the GPIO ports (which were named GPIO_0) to a led and 3 buttons, so you will have to mod
  14. Hello, Sorry for the delayed answer. I have managed to replicate the error using the same hardware setup as described, and it is thrown when I try to program the board while JP5 is set on QSPI. Can you try moving the jumper from QSPI to JTAG, as in the photo, and then program the board again? For me this fixed the issue. Best wishes, Eduard
  15. Hello @rt54321, According to the Xilinx's Zynq-7000 SoC Technical reference manual(https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf#G16.360722 ) you can program the trigger sensitivity using the INT_TYPE, INT_POLARITY and INT_ANY registers. In the reference manual you may also find useful 14.3.4 Reading Data from GPIO Input Pins; Option 2: Use interrupt logic on input pins and Appendix B.19 General Purpose I/O Register Details (gpio) Best wishes, Eduard
  16. Hello, Your idea is indeed correct, alternating between the displays really fast gives the illusion that both are turned on at the same time. As of implementing it, you could do something similar to this pseudocode selection <- read selection bit while(program runs){ data0 <- aquire digit value for display 0 data1 <- aquire digit value for display 1 display0 <- translateData(data0) // translate data0 into a seven segment encoding display1 <- translateData(data1) // translate data1 into a seven segment encoding if(selection == 0) then write display0 to data bits of the
  17. Hello, Here are some of our boards that utilize the HDMI interface, alongside the reference manual and demos similar to what you are looking for: Zybo-Z7 https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/ https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start Arty-Z7 https://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/ https://reference.digilentinc.com/reference
  18. Hello @aams, We have a very similar project for the Zybo Z7 that you can access here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start Best wishes, Eduard
  19. Hello @Kyle_ISL, Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format. For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here: https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf
  20. Hello @Marycruz, Firstly, I have also encountered the vivado launcher error from time to time. It is nothing serious and can be ignored. Secondly, Vivado and the SDK can have problems if the paths to the project contain whitespaces https://www.centennialsoftwaresolutions.com/post/xilinx-sdk-internal-error-the-folder-c-metadata-is-read-only I would recommend extracting the project in a folder that does not contain whitespace such as "Marycruz_Blas_Hder" or something equivalent. Best wishes, Eduard
  21. Hello @aams, Was the project working before on the zedboard? Or are you talking about the HLS ip? If the HLS testbench results were correct, maybe the problem is the clock period with which the design was constrained. Can you tell me the clock period of the HLS ip? Can you also attach the HLS code? Thanks, Eduard
  22. Hello, Are you sure that everything is okay with the new .bin file? From what I recall, boot.bin consists of .bit & .elf files. Maybe there have been changes to the .bit file which affect the behaviour of the GPIO. Best wishes, Eduard
  23. Hello @rajareanne, I would say it is possible to use the DDR to write a long sequence representing the sine wave. For streaming purposes, I think it would be best for you to use a DMA module. I have found this demo, which does something quite similar to what you are looking for https://www.hackster.io/whitney-knitter/sine-wave-generation-in-c-on-zynq-e442e4 Best wishes, Eduard
  24. Hello @mehmet, Vitis does not come with example hardware platform for our boards by default. If you want to reuse the platform multiple times and not have to search for it in Vitis every time, you can add it to Xilinx\Vitis\<your_version>\data\embeddedsw\lib\fixed_hwplatforms. For example, I added a platform named system_wrapper.xsa to the folder and it appeared as in the photo listed below. If you want to try out some existing demos for the Nexys Video that make use of the Microblaze, you can check out these: https://reference.digilentinc.com/reference/programmable-logic/nexys-vide
  25. Hello @[email protected], Have you modified the hls_helper file found on github? In your screenshot I see that the errors occurs at different lines when compared to the github source file. Have you perhaps changed the inR, inG, inB from xf::Mat to ap_uint<8>?