Niță Eduard

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  1. Hello, Sorry for the delayed answer. I have managed to replicate the error using the same hardware setup as described, and it is thrown when I try to program the board while JP5 is set on QSPI. Can you try moving the jumper from QSPI to JTAG, as in the photo, and then program the board again? For me this fixed the issue. Best wishes, Eduard
  2. Hello @rt54321, According to the Xilinx's Zynq-7000 SoC Technical reference manual(https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf#G16.360722 ) you can program the trigger sensitivity using the INT_TYPE, INT_POLARITY and INT_ANY registers. In the reference manual you may also find useful 14.3.4 Reading Data from GPIO Input Pins; Option 2: Use interrupt logic on input pins and Appendix B.19 General Purpose I/O Register Details (gpio) Best wishes, Eduard
  3. Hello, Your idea is indeed correct, alternating between the displays really fast gives the illusion that both are turned on at the same time. As of implementing it, you could do something similar to this pseudocode selection <- read selection bit while(program runs){ data0 <- aquire digit value for display 0 data1 <- aquire digit value for display 1 display0 <- translateData(data0) // translate data0 into a seven segment encoding display1 <- translateData(data1) // translate data1 into a seven segment encoding if(selection == 0) then write display0 to data bits of the
  4. Hello, Here are some of our boards that utilize the HDMI interface, alongside the reference manual and demos similar to what you are looking for: Zybo-Z7 https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/ https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start Arty-Z7 https://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/ https://reference.digilentinc.com/reference
  5. Hello @aams, We have a very similar project for the Zybo Z7 that you can access here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start Best wishes, Eduard
  6. Hello @Kyle_ISL, Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format. For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here: https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf
  7. Hello @Marycruz, Firstly, I have also encountered the vivado launcher error from time to time. It is nothing serious and can be ignored. Secondly, Vivado and the SDK can have problems if the paths to the project contain whitespaces https://www.centennialsoftwaresolutions.com/post/xilinx-sdk-internal-error-the-folder-c-metadata-is-read-only I would recommend extracting the project in a folder that does not contain whitespace such as "Marycruz_Blas_Hder" or something equivalent. Best wishes, Eduard
  8. Hello @aams, Was the project working before on the zedboard? Or are you talking about the HLS ip? If the HLS testbench results were correct, maybe the problem is the clock period with which the design was constrained. Can you tell me the clock period of the HLS ip? Can you also attach the HLS code? Thanks, Eduard
  9. Hello, Are you sure that everything is okay with the new .bin file? From what I recall, boot.bin consists of .bit & .elf files. Maybe there have been changes to the .bit file which affect the behaviour of the GPIO. Best wishes, Eduard
  10. Hello @rajareanne, I would say it is possible to use the DDR to write a long sequence representing the sine wave. For streaming purposes, I think it would be best for you to use a DMA module. I have found this demo, which does something quite similar to what you are looking for https://www.hackster.io/whitney-knitter/sine-wave-generation-in-c-on-zynq-e442e4 Best wishes, Eduard
  11. Hello @mehmet, Vitis does not come with example hardware platform for our boards by default. If you want to reuse the platform multiple times and not have to search for it in Vitis every time, you can add it to Xilinx\Vitis\<your_version>\data\embeddedsw\lib\fixed_hwplatforms. For example, I added a platform named system_wrapper.xsa to the folder and it appeared as in the photo listed below. If you want to try out some existing demos for the Nexys Video that make use of the Microblaze, you can check out these: https://reference.digilentinc.com/reference/programmable-logic/nexys-vide
  12. Hello @[email protected], Have you modified the hls_helper file found on github? In your screenshot I see that the errors occurs at different lines when compared to the github source file. Have you perhaps changed the inR, inG, inB from xf::Mat to ap_uint<8>?
  13. The link will redirect you to this website https://mautic.digilentinc.com/adept-system-download Fill in the form and the download should start automatically.
  14. Strange, I seem to be able to download it I have attached the zip file from the download section libCseDigilent_2.5.2-x86-x64-Windows.zip
  15. Hello @Han_newbie, Try to download the Digilent Plugin Tool from here: https://reference.digilentinc.com/reference/software/digilent-plugin-xilinx-tools/start On the lower page you should find the zip archives: