Niță Eduard

Basically, if you want to make changes to what was auto-generated based on the xsa/hdf, you can do so by modifying system-user.dtsi. So you don't have to always modify it, only when you want to change something.

Hello @thoonky, I don't think the 2017.4 version of the demo is compatible with Petalinux 2021.2. If you want to use the 2017.4 demo, you should use Petalinux 2017.4. We have an upgraded version of the project for Petalinux 2021.1, which can be found here https://github.com/Digilent/Cora-Z7-OS/tree/07S/Petalinux/upgrade , on the upgrade branch. I have also attached a bsp file of the 2021.1 project. Best wishes, Eduard cora-z7-07.bsp

Hello @Antonio Fasano, Can you try to make the following edits on your makefile? https://support.xilinx.com/s/article/75527?language=en_US I remember having these issues when moving from SDK to Vitis 2020.1. However, when moving from Vitis 2020.1 to Vitis 2021.1, we also encountered makefile issues, and these were fixed by making the following change (in addition to the ones from SDK->Vitis): https://github.com/Digilent/vivado-library/commit/0390827da381069bf0c0a7f46584bcaaadc3ca01#diff-bb9af5d1915da1fbc132ced081325efcd2e63e4804f96890f42e9739677237a4 Hope you find these changes

Usually undefined reference to main occurs when the main() function does not exist in the program. Can you verify that you have a main() function in your code? If you do have a main() function in your files, can you post your source files?

Hello @rmccormack1, What version of Vitis are you using? Also, besides the makefile error are there any other errors in the console? Can you provide the messages from the build console? Best wishes, Eduard

Hello @miezekatzen_dompteur, In the beginning of that tutorial it is stated that a license for the TEMAC IP is required. Have you followed this guide on how to obtain a license for it? https://reference.digilentinc.com/vivado/temac Best wishes, Eduard

Hello @lukelouyu, Do you use an external power supply? I have found these forum posts with a similar issue which were fixed by a) switching the micro-USB cable b) changing the power supply Best wishes, Eduard

Hello, Can you post the source of your UART implementation? Also, does your implementation use any parity bits? In my case, using a parity bit made the terminal also display garbage. Best wishes, Eduard

Hello, Sorry for the late reply. Perhaps using a pipeline directive to write the data in burst mode may fix the issue. Take a look at these code snippets. I'm not sure how HLS will handle the switch statement, but from the page linked above it states that: So an issue may also be caused by this. Maybe try to only send the data without the switch statement and see if the constants are sent correctly. Best wishes, Eduard

Hello @Muhammed Kawser Ahmed, We currently do not have an example for software image processing for the Pcam project. This HDMI Input/Output project does software processing, which could be used as a starting point, if you need software image processing. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-hdmi-demo/start However, edge detection would be slow if implemented using the processor. We also have the Embedded Vision Workshop, which guides you to create a demo which takes Pcam image data as input, processes it using a Sobel Edge Detection IP (whi

Hello @Engr_Shan, We have several example projects which use the XADC IP. I'm not sure what board you have, but you if you want an HDL-only project, you can look at the following: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-xadc-demo/start where the LED associated with a channel brightens as that channel's voltage increases https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-xadc/start where the 7-segment displays show the voltage difference If you want to use it with a Zynq processor, you can check out this demo: https://refer

Hello @seaover, The error you are encountering is very similar to the one described in this post on the Xilinx forum . Can you try to modify your makefile according to the process described in that thread? Also, take a look at this answer record, which is related to that post. Best regards, Eduard

Hello @Zakir Hussain, These warnings appear in versions of Vivado greater than 2017.4. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted.  You can ignore these warning, since for Zynq based designs they won't cause any issues. For more information regarding the warning, please see this section of the reference manual. Best wishes, Eduard

Hello @rt54321, You can use the commands mrd and mwr in the XSCT (Xilinx Software Command line Tool) to read/write values from/to registers. You can find the documentation for these here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1208-xsct-reference-guide.pdf Although not related to the project, here is a tutorial which debugs a VDMA IP using XSCT commands on registers: https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-25-Debugging-issues-on-the-AXI-VDMA-IP/ba-p/941372 You could try clearing the interrupt pending register, which

Hello @rt54321, From what I can tell, you implemented the button connection using the "Connect board component" option. This forces the AXI GPIO to be configured as "All inputs". I would recommend disconnecting the AXI GPIO from the board sidebar, reconfiguring the AXI GPIO to allow both inputs & outputs and then making the port of the AXI GPIO external (and after that creating an .XDC and constraining your ports). The XDC would look similar to this (Disclaimer: I have used a ZYBO Z7 to constrain the GPIO ports (which were named GPIO_0) to a led and 3 buttons, so you will have to mod