joestoy

If I program the flash on my ArtyA7-100 in the standard way, with a bitstream starting at address 0 and an elf file starting at address 0x40_0000 (using the program_flash script attached), everything works just fine. vivado_lab reports ------ Performing Erase Operation... Erase Operation successful. Performing Program and Verify Operations... Program/Verify Operation successful. INFO: [Labtoolstcl 44-377] Flash programming completed successfully ------ the bitstream can be successfully loaded into the FPGA (if JP1 is appropriately set), and anywhere in the 16MB address space can be successfully read by the AXI4 interface. So far so good. If I subsequently erase the entire flash (using the erase_flash script, also attached), again vivado_lab reports "Erase Operation successful", but now the AXI4 interface sees every byte as 0xCC, rather than the expected 0xFF. Is this expected? If not, what can I do about it? In the longer term I wish to use the entire flash for fixed data (loading the bitstream via JTAG). I hope to write just one datafile beginning at address 0 (e.g. by using the "datafile" clause in the program_flash script). Is this supposed to work? If I try this now, again vivado_lab reports "Program/Verify Operation successful", but again every byte is 0xCC rather than my expected data. Any advice or help much appreciated! My board is serial DAE1AFF. The vivado_lab used is 2022.2. The bitstream was synthesized by Vivado 2019.1 using a block design and running at 25MHz. The flash is controlled by the "AXI Quad SPI (3.2)" IP (IP Interface: SPI, Board Interface: qspi flash, XIP mode enabled, Mode: Quad, Slave Device: Spansion; .xdc constraints as generated by Vivado). Please let me know if I've omitted any relevant information. Thanks joe program_flash erase_flash