idraney

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Everything posted by idraney

  1. Hi @JColvin, Thank you for responding. The XML data in the board files was definitely helpful to finally finding a solution. The difficult part was configuring the tristate buffer in the Verilog code properly (and remembering to disable Vivado management of the top level wrapper!). Here is a little snippet of what I did in the top level Verilog code to interact with the SRAM chip's data pins: /////////////////////////////////////////////////////////// // SRAM Data IOBUF Instantiation genvar index; generate for (index = 0; index < 8; index = index + 1)
  2. Hello Digilent Forum! I have been able to run the Cmod A7 Out of Box Demo and export it to an SDK/Vitis project, then modify memorytest.c to write and read new data to and from the SRAM. What a great demo for getting started with the Cmod A7! However, I would like to configure the external memory controller (AXI EMC) block to use its individual ports -- without using the Cmod A7 board file and the "cellular_ram" port from the EMC_INTF pin of the EMC block. I created a new project that uses the xc7a35tcpg236-1 FPGA (not the board file), edited the constraints XDC file, and pinn