How to make clear clock using clk_wiz in FPGA Posted July 23 Hi, All I'd like to create a frequency with an interval of 1 MHz, such as 6,7,8,9,10,11,12 MHz now. I made it like this (attached files), but it doesn't come out properly. When the created frequency is measured using the oscilloscope, the shaking occurs greatly. I need a sophisticated frequency that doesn't shake. Is there a way? Unlike the attached photo, the ENALBE I/O lock and reset were not checked. Thanks
How to make clear clock using clk_wiz
in FPGA
Posted
Hi, All
I'd like to create a frequency with an interval of 1 MHz, such as 6,7,8,9,10,11,12 MHz now.
I made it like this (attached files), but it doesn't come out properly.
When the created frequency is measured using the oscilloscope, the shaking occurs greatly.
I need a sophisticated frequency that doesn't shake. Is there a way?
Unlike the attached photo, the ENALBE I/O lock and reset were not checked.
Thanks