I have been working with Intel/Altera FPGA for several years now. I recently bought a Zybo-Z7-20 (July 2020)
because I am interested using the Zynq ARM+FPGA SoC for solving contemporary problems.
To get started, I tried to follow your instructions at https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
Unfortunately, I cannot get any Project running without errors in Vivado, Vitis or Petalinux.
Most of the given tcl scripts don't succeed to create Vivado project files, and even if this works,
I tried Vitis 2020 and event the hopelessly outdat