Jump to content

charkster

Members
  • Posts

    12
  • Joined

  • Last visited

Everything posted by charkster

  1. I decided to configure one XADC resource to be DRP interface, single channel, event triggered with adc_clk being 4 dclk cycles. No averaging, adc offset and gain correction, sensor offset and gain correction (sensor is probably not needed). Vaux4 selected. I am able to enable/disable the adc with a config register. I start the first conversion with a rise edge detect of the config register and then the eoc_out triggers until the config register is written low. Constraints ## Analog XADC Pins ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12 set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { vauxn4 }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15] set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { vauxp4 }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15] #set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16] #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16] RTL file: assign adc_trigger = (cfg_enable && eoc_out) || pos_edge_enable; xadc_wiz_0 u_xadc_wiz_0 // DRP single channel event triggered 4 clocks, no averaging, adc offset and gain correction, sensor offset and gain correction, no alarms, ( .convst_in (adc_trigger), // input .daddr_in (7'h14), // input [6:0] address x14 is Vauxp4/Vauxn4 result .dclk_in (clk_250mhz), // input .reset_in (~rst_n_250mhz), // input .di_in (16'd0), // input [15:0] .dwe_in (1'b0), // input .den_in (1'b0), // input .do_out (adc_data), // output [15:0] .drdy_out (adc_ready), // output .busy_out (busy), // output .channel_out (), // output [4:0] .eoc_out, // output .eos_out (), // output .alarm_out (), // output .vauxp4, // input analog .vauxn4, // input gnd .vp_in (), // input, board schematic has this at anaground .vn_in () // input, board schematic has this at anaground );
  2. Hi @JColvin, Thank you very much!! I should have looked at the schematic. I raised pin 15 voltage to 3.3V and saw full range on the 12bit value. I have a really good XADC configuration which is working well for me. I will post it tomorrow if others are interested. It converts a single channel continuously and has a data valid signal.... very simple. Great support is why my company buys Digilent.
  3. After looking at ug475_7Series_Pkg_Pinout.pdf page 98 (CPG236) pins G2, G3, J2 and H2 are able to connect to any AD0P/AD0N−AD15P/AD15N signal. In looking at the default pin constraint file for the cmod a7, there is a comment for using pins 15 and 16: ## Analog XADC Pins ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12 #set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15] #set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15] #set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16] #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16] I will try to specifically use vaux4. Are the G2 and G3 pins both tied to pin 15? Are G2 and J2 tied to analog ground? If they are, why would they appear in the pin constraint file? Thanks.
  4. I have read UG480. It looks like only specific sequencer channels can be used with the 2 pins which are available on the cmod a7. Does anyone know which channels can be used? I have tried Vp/Vn but this does not appear to give me the results I expected. I am putting 0.2V on the analog input and am expecting a 12bit value of 820 decimal. Also, I was expecting the XADC Wizard to allow a static configuration where the channel_out[4:0] could be tied to the daddr_in[6:0] and the do_out[15:0] would always show valid channel conversion values when the busy_out is low. I have seen examples of the eoc_out signal being tied to the den_in input which looks like a good way to keep the sequencer always running. https://sites.google.com/a/umn.edu/mxp-fpga/home/vivado-notes/xadc/single-channel-continuous-mode-example I was not able to get this working, but it appears to be the simplest/best way to configure the XADC. Does anyone have this method working? Thanks.
  5. I was able to program the spi flash memory on the cmod a7 by compiling xc3sprog from source on my raspberry pi. Here are the steps I used: (1) install libftd2xx drivers download libftd2xx-arm-v7-hf-1.4.22.gz and follow instructions in ReadMe.txt (2) Download xc3sprog from github sudo apt update sudo apt install build-essential libusb-dev libftdi-dev libgpiod-dev wiringpi git cmake git clone https://github.com/matrix-io/xc3sprog (3) Modify progalgspiflash.cpp add case 0x16: case 0xba: fprintf(stderr, "Found Numonyx N25Q Device, Device ID 0x%02x%02x\n", fbuf[1], fbuf[2]); switch (fbuf[2]) { case 0x16: pages = 16384; sector_size = 65536; break; (4) Compile xc3sprog mkdir xc3sprog/build cd xc3sprog/build cmake .. make sudo make install (5) Run the program command with the "-I" option, using the attached first.bit to help detect the spi flash rom. xc3sprog -c jtaghs1_fast -Ifirst.bit xc3sprog -c jtaghs1_fast -I your_design.bit Works like a charm. I have attached the xc3sprog compiled to run on raspberry pi (it still needs the libftdi1 library to be installed... sudo apt-get install libftdi1). first.bit run_first_spi_flash_cmod_a7.sh xc3sprog The first.bit file was created by taking this VHDL design from the github xc3sprog repo: xc3sprog/bscan_spi/bscan_xc7_spi.vhd and making it into a bit file using Vivado (with the target being the CMOD A7 board). I have included the constrants file "constr.xdc" which I used to create the first.bit file. constr.xdc
  6. I did find the page which describes the approach that @xc6lx45 suggested. https://www.eevblog.com/forum/microcontrollers/alinx-ax309/ I found the Micron datasheet for the specific flash memory: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf?rev=27fc6016fc5249adb4bb8f221e72b395 I searched for "JEDEC", but could not see any thing that relates to "20 ba" hex. @xc6lx45 you were right about the need to modify xc3sprog source code to get this memory supported. Thanks for all your help... I will pick up this effort at a future date. Just being able to program the FPGA is good for now.
  7. @JColvin, thank you for the details. I will look closer at the vhdl program to see what it is doing. I made some progress by using the xc3sprog "-I" option. The first (xc3sprog) design is definitely helping the Flash memory to be detected! I'm not sure what the "ISF Bitfile" is. xc3sprog -c jtaghs1_fast -I design.bit XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 774 $ OS: Linux Free software: If you contribute nothing, expect nothing! Feedback on success/failure/enhancement requests: http://sourceforge.net/mail/?group_id=170565 Check Sourceforge for updates: http://sourceforge.net/projects/xc3sprog/develop Using Libftdi, JEDEC: 20 ba 0x16 0x10 Found Numonyx N25Q Device, Device ID 0xba16 Unexpected N25Q size ID 0x16 ISF Bitfile probably not loaded I have tried writing bit, mcs and hex files (converted using Vivado) but here is the result that I get: xc3sprog -c jtaghs1_fast -I design.hex:w:0:MCS XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 774 $ OS: Linux Free software: If you contribute nothing, expect nothing! Feedback on success/failure/enhancement requests: http://sourceforge.net/mail/?group_id=170565 Check Sourceforge for updates: http://sourceforge.net/projects/xc3sprog/develop Using Libftdi, JEDEC: 20 ba 0x16 0x10 Found Numonyx N25Q Device, Device ID 0xba16 Unexpected N25Q size ID 0x16 ISF Bitfile probably not loaded I found this webpage which completely describes my situation... the Unexpected N25Q size ID 0x16, but their solution does not look applicable to me. The memory size should be 4MB. sourceforge xc3sprog to N25Q flash memory
  8. @xc6lx45 Thanks! I have made the new bit file (I called it "xc3sprog_first.bit"). No problems that I could see with the pin constraints file... I checked the log file. I am able to load it into the CMOD A7 and I see the RED led on. I am not seeing anything new when running djtgcfg enum or xc3sprog -c jtaghs1_fast Also, I had to guess on the MISO_ext pin in the constraints file... it connects to "qspi_dq[1]" in the schematic. Not sure if that is correct. Thanks again.
  9. Thanks @JColvin & @xc6lx45 ! I am new to Adept and xc3sprog so I thought I would ask. @xc6lx45, I am assuming that programming your design will allow xc3sprog to detect the flash scan chain or is the flash memory also programmed when I program the FPGA? Thanks again... I don't mind a 2 step process. In looking at the pin constraints file, I am assuming that I will need to map MOSI_ext, MISO_ext, IO2, IO3 and CSB_ext to the proper pins of the CMOD A7 board. CMOD A7 board schematic Github pin constraints for CMOD A7 Here are my pin constrain changes for CMOD A7: # ################################################# # RED LED # ################################################# #set_property PACKAGE_PIN M16 [get_ports RLED] #set_property IOSTANDARD LVCMOS33 [get_ports RLED] set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { RLED }]; #IO_L14P_T2_SRCC_16 Sch=led0_r # ################################################# # dummy green LED # ################################################# #set_property PACKAGE_PIN M18 [get_ports GLED] #set_property IOSTANDARD LVCMOS33 [get_ports GLED] set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { GLED }]; #IO_L13N_T2_MRCC_16 Sch=led0_g # ################################################# # SPI MOSI # ################################################# #set_property PACKAGE_PIN K17 [get_ports MOSI_ext] #set_property IOSTANDARD LVCMOS33 [get_ports MOSI_ext] set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { MOSI_ext }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] # ################################################# # SPI MISO # ################################################# #set_property PACKAGE_PIN K18 [get_ports MISO_ext] #set_property IOSTANDARD LVCMOS33 [get_ports MISO_ext] set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { MISO_ext }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] # ################################################# # SPI WP/IO2 # ################################################# #set_property PACKAGE_PIN L14 [get_ports IO2] #set_property IOSTANDARD LVCMOS33 [get_ports IO2] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { IO2 }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] # ################################################# # SPI HOLD/RESET/IO3 # ################################################# #set_property PACKAGE_PIN M14 [get_ports IO3] #set_property IOSTANDARD LVCMOS33 [get_ports IO3] set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { IO3 }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] # ################################################# # SPI CS # ################################################# #set_property PACKAGE_PIN L13 [get_ports CSB_ext] #set_property IOSTANDARD LVCMOS33 [get_ports CSB_ext] set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { CSB_ext }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]
  10. Hi, I am able to program my CMOD A7-35t FPGA using either Adept 2 or xc3sprog. Using Adept 2 (after downloading and installing the runtime and utility deb files): djtgcfg enum djtgcfg prog -d CmodA7 -i 0 -f design.bit Using xc3scprog (after sudo apt-get install xc3sprog): xc3sprog -c jtaghs1_fast -T xc3sprog -c jtaghs1_fast design.bit I am not able to see a flash device with either Adept 2 or xc3sprog. All I can see is one device, the FPGA. Is there a way to program the flash memory with either Adept 2 or xc3sprog? Thanks. I created the MCS files... would I need to use openocd through the FT2232H on the cmod a7? Is there a template for writing to the Micron memory?
×
×
  • Create New...