chrisn

Newcomers
  • Content Count

    3
  • Joined

  • Last visited

  1. I was able to solve the problem. In the implemented design you need to ensure that the Vcco column doesn't show any 2.5V in i/o bank 35. Mixing LVDS_25 and TMDS_33 in the same bank is possible.
  2. I've been digging through the pcam5 example project and it does seem to map the hdmi to bank 35 along with the mipi csi-2. I can build the default project, but if I upgrade the project to 2020.1 it complains about the voltage levels as well. Its my understanding that you can't have multiple voltage levels on the same bank. Is this one of those things that can be safely ignored? Is there a way around this error in Vivado? I'm still confused how this works in the example project. Removing sys_clk, and hdmi. I'm able to successfully generate a bitstream. I'll need to figure out how to verify things are working without hdmi out.
  3. Hi I'm trying to get a minimal mipi csi-2 design working using the new free IP in vivado 2020.1. I have a synthisizeable design, but I'm having issues with sys_clock and mipi signals being incompatible voltages. I've been using the digilent 2019.1 pcam project as a reference, but I cant seem to find how to configure sys_clock not to interfere with the 2.5v mipi signals. I have the xdc file from the pcam demo imported into 2020.1 [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: sys_clock (LVCMOS33, requiring VCCO=3.300) and dphy_data_hs_p[0] (LVDS_25, requiring VCCO=2.500)