I was able to find the issue. PG_MODULE was being driven too low and I fixed the offending portion.
This might be helpful for others experiencing something similar. What I actually saw on JTAG was it resetting and going into Shift-DR. Then, the FPGA's IDCODE was shifted out, then zeroes. When tracing this on the FMC v2 carrier, I noticed the ARM IDCODE coming after. The PL was clearly being powered on my carrier and the PS supplies are all on the picozed, except for 5V and PG_MODULE. Then I noticed PG_MODULE (connected to PS_POR_B) was not high enough and fixed it.