Sean Kelly

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  1. Thank you so much. That makes sense, but what does not make sense is that the datasheet states to pullup 2.5V signal lines to 3V3. The Cora on the other hand did what I would have thought and that is tie the PUs to the bank voltage being used. Thoughts? I am guessing it was an oversight on the datasheet writer.
  2. Can anyone explain why the dev kit has 4k7 pull ups on the RxD 0-3 lines? I can't find anything in the PHY datasheet to indicate the need and I have never seen this done before. Thanks.
  3. Thank you for the help and insight.
  4. I find that there being a need for a series resistor of that magnitude to match a 40 ohm TL to bring the signalling into compliance and yet Xilinx not thinking that DCI is needed to bring the output impedance closer to 40 ohms and hence not having a need for the 22 ohm part quite difficult to comprehend. Especially since they have it for DDR2. Any thoughts as to why they would have removed the option? Please keep in mind my expertise is in PCB layout and not FPGAs so I am learning more about them. By the way, is it possible to get the gerber files for the Cora dev kit?
  5. So basically the validation/simulation found the driving impedance to be ~18 ohms on the Zync Bank 502 outputs?
  6. Hello elodg, thank you for the help. So if I understand you correctly, Digilent feels that the drive needs impedance matching but Xilinx does not? Why would all of your other dev kits with the Xilinx parts not need the series termination but the Zync does? Any insight would be really appreciated.
  7. I noticed that on the Cora dev kit there are series termination resistors on the address and control nets and wondering why. Does not Bank 502 not have the ability to use DCI to create the 40 ohm output impedance? Why are the VRP/VRN resistors 80 ohms instead of 40? Thanks, Sean
  8. Sean Kelly


    On the Artix 7 we used an EMCCLK for faster communication with the QSPI. I don't see anything like that in the Zync 7010. Is there a similar setup available for the Zync? Thanks, Sean
  9. Hello, I am trying to figure out where I find the pin length/delay when connecting the QSPI to the Cora Z7 - 7010 SoC. When connection are made to a normal FPGA, my coder can get that info from Vivado. How do we get that information when on the PS side of the SoC? We am using the XC7Z010-1CLG400C part. Thanks for any help. BTW, I am a HW engineer working on the layout.
  10. Thank you. I did not catch that the bytes were swapped too.
  11. Hello, The schematics for the Cora Z7 dev kit shows the DQS 0 and 1 swapped on the FPGA. Anyone have an idea why? DQS0 should be on B2/C2 but is tied to F2/G2. DQS1 should be on F2/G2 but is on B2/C2.
  12. Thank you for the quick reply.
  13. Hello, we are wanting to incorporate most of the Cora Z7 dev kit design into our project and I was wondering if you would be willing to share the schematic and PCB design files. Thanks, Sean