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  1. Norbert96

    ADC FPGA connection

    Hi! I have been working on a digital filter in LabVIEW for and ADC called AD7402. Can somebody explain the following codesequence? I don't understand what it does. I can find all the code in the datasheet of the ADC in the attachments. WORD_CLK = output word rate */ always @ (negedge word_clk ) begin case ( dec_rate ) 16'd32:begin DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; end 16'd64:begin DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; end 16'd128:begin DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFF
  2. Hi! I want to read the output data of a delta-sigma modulation based ADC (AD7402) using NI LabVIEW FPGA. Can you help me by explaining what the Verilog code in the attached datasheet (page 17) does? AD7402.pdf