CPerez10

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Everything posted by CPerez10

  1. Didn't know those were pullup constrains, thanks for letting me know. Now the clock seems to tick regardless of whether I place the keyboard in though. And when I set the constraints to the values they should be for coding, it still doesn't work. Thoughts?
  2. I'm aware of the UCF constraint discrepancy, I mentioned that I used both the clocks in the clk/data pins to check both the clocks and ignore the data line (this way I could check both at once and cover my bases faster). If you notice, I have the correct values commented out. So this isn't the error.
  3. Took a look at the code. There's nothing there (or anywhere else) that indicates having to do anything in order to get the clock on the device going. In my latest attempt, I set the UCF file to include the clocks from both ports in the clock and data lines respectively (just to cover all my bases). I tried hooking up 3 different keyboards (all of which work and have various specs) to either side and looked at the clock. Not a blip. Here's a small snippet of the relevant code: begin clk_div_inst : clk_div port map( CLK_IN => clk, CLK_OUT => div_clk); process(div_clk, USB2_CLK) begin end process; dio0 <= USB2_CLK; dio1 <= USB2_DATA; dio2 <= div_clk; end Behavioral; NET clk LOC=D11; #NET USB2_CLK LOC=K17; #NET USB2_DATA LOC=L17; NET USB2_CLK LOC=A12; NET USB2_DATA LOC=k17; NET led<0> LOC=W3; NET led<1> LOC=Y4; NET led<2> LOC=Y1; NET led<3> LOC=Y3; NET led<4> LOC=AB4; NET led<5> LOC=W1; NET led<6> LOC=AB3; NET led<7> LOC=AA4; NET dio0 LOC=AB20; #BB1 etc. NET dio1 LOC=P17; NET dio2 LOC=P18; Only thing I can think of now is that there's something wrong with my UCF file, but I also saw the lines going up/down when I was configuring them to get the clock started, so I kind of doubt it.
  4. Thanks for pointing out that I can use the Vivado simulator, I didn't think about it since I had to use ISE to run on the Spartan 6. Turns out my code just needed to wait for one more clock cycle for the output to route to the LEDs.
  5. I know this topic has been started before, but I wanted to program my own driver to communicate with the keyboard as a learning experience. Currently trying to get data from my USB keyboard or getting the clock going. I used this guide: http://www.burtonsys.com/ps2_chapweske.htm According to the guide, I simply need to leave the clock high for 50 microseconds. I've tried various permutations of manipulating the clock and data line on the rising/falling edge, but not a single blip that I haven't caused. I'm using waveforms to see if any of the lines move. Only my div clock does (10Khz). library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_unsigned.all; entity KeyMain is Port (clk : in STD_LOGIC; USB2_CLK : inout STD_LOGIC; USB2_DATA : inout STD_LOGIC; led : out STD_LOGIC_VECTOR(7 downto 0); dio0 : out STD_LOGIC; dio1 : out STD_LOGIC; dio2 : OUT STD_LOGIC); end KeyMain; architecture Behavioral of KeyMain is component clk_div is port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end component; signal key_buff : STD_LOGIC_VECTOR(7 downto 0) := "10000001"; signal buff_counter : unsigned(3 DOWNTO 0) := "0000"; signal temp : STD_LOGIC := '0'; signal step_counter : unsigned(3 DOWNTO 0) := "0000"; signal div_clk : STD_LOGIC; begin clk_div_inst : clk_div port map( CLK_IN => clk, CLK_OUT => div_clk); process(div_clk, USB2_CLK) begin if falling_edge(USB2_CLK) then if step_counter = 1 then if buff_counter > 10 then buff_counter <= "0000"; --key_buff <= "00000000"; else buff_counter <= buff_counter + 1; end if; if buff_counter > 0 then key_buff(to_integer(buff_counter - 1)) <= USB2_DATA; end if; end if; end if; if falling_edge(div_clk) then if step_counter = 0 then USB2_CLK <= '1'; --USB2_DATA <= '1'; --elsif step_counter = 1 then --USB2_CLK <= '0'; --USB2_DATA <= '0'; --elsif step_counter = 2 then --USB2_DATA <= '0'; end if; if step_counter /= 1 then step_counter <= step_counter + 1; end if; end if; end process; led <= key_buff; dio0 <= USB2_CLK; dio1 <= USB2_DATA; dio2 <= div_clk; end Behavioral;
  6. Hey guys. Still in the noob state where I'm overlooking something simple, but I've tried searching quite a bit on the web to no avail on using the block RAM properly. I use the IP core generator to create a 32x64512 bit block RAM. I then created a simple example that should light my LEDs with the contents I recently wrote into the RAM. No lights light up. Here's the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity MainSPI is Port ( clk : in STD_LOGIC; led : out STD_LOGIC_VECTOR (7 downto 0)); end MainSPI; architecture Behavioral of MainSPI is component Block_RAM port( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR(0 downto 0); addra : in STD_LOGIC_VECTOR(15 downto 0); dina : in STD_LOGIC_VECTOR(31 downto 0); douta : out STD_LOGIC_VECTOR(31 downto 0) ); end component; signal flip1 : STD_LOGIC := '0'; signal flip2 : STD_LOGIC := '0'; signal ram_addr : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000"; SIGNAL write_enable : STD_LOGIC_VECTOR(0 downto 0) := "0"; signal ram_write : STD_LOGIC_VECTOR(31 DOWNTO 0); signal ram_read : STD_LOGIC_VECTOR(31 DOWNTO 0); begin ram_instance : Block_RAM port map( addra => ram_addr, wea => write_enable, dina => ram_write, douta => ram_read, clka => clk ); process(clk) begin if rising_edge(clk) then if flip1 = '0' then write_enable <= "1"; ram_addr <= "0111110000000000"; ram_write <= "10101010111111110000100011101111"; flip1 <= '1'; end if; if flip2 = '0' and flip1 <= '1' then write_enable <= "0"; ram_addr <= "0111110000000000"; led <= ram_read(11 downto 4); flip2 <= '1'; end if; end if; end process; end Behavioral;
  7. I looked up the reference manual and it seems that the QSPI flash provided is only for configuration of the FPGA. Is there any way to access it? I looked at the master UCF and couldn't find the pins for it.
  8. Went through the code. It does indeed work, thank you. This raises a few questions though. Are VHDL logic vectors stored as little endian, or just iterated backwards? And is there a book/website on timing with VHDL? The button synchronization needs a bit of an explanation.
  9. Oh, and it's standard polarity, 8 data bits, no parity, and 1 stop bit. Also, I noticed I left some artifacts from other attempts (int_tick and other commented division constant). Apologies.
  10. Title says it all. I've tried various baud rates. I've tried using the wizard to generate a clock that I then divide to see if it's more accurate. Right now, the latest attempt divides my 100MHz clock by 1k to get a clean 100k baud. I'm using the analog discovery 2 to spy on BB1 (first breadboard pin) on my Anvyl. My code waits for a button press to repeatedly send out a simple hard-coded message, which then resets on the button release. The LEDs are just for primitive version control (so I know what program is on the board). Here's the source for both the repeater and the clock divider: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; entity msg_repeater is Port ( clk : in STD_LOGIC; btn : in STD_LOGIC; tx : out STD_LOGIC; led : out STD_LOGIC_VECTOR (3 DOWNTO 0)); end msg_repeater; architecture Behavioral of msg_repeater is component clk_div is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end component; -- Binary message content: -- "01010100" T -- "01000101" E -- "01010011" S -- "01010100" T -- "00100000" space (0 and 1 added on sides of each character for UART protocol) signal msg : std_logic_vector (49 downto 0) := "00101010010010001011001010011100101010010001000001"; signal msg_index : natural range 0 to 50 := 0; signal int_tick : std_logic := '0'; signal baud_tick : std_logic := '0'; begin clk_div_inst : clk_div port map( CLK_IN => clk, CLK_OUT => baud_tick ); process(baud_tick) begin if rising_edge(baud_tick) then if(btn = '1') then if(msg_index = 50) then msg_index <= 0; end if; tx <= msg(msg_index); msg_index <= msg_index + 1; else tx <= '1'; msg_index <= 0; end if; end if; end process; led <= "1010"; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clk_div is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end clk_div; architecture Behavioral of clk_div is --signal clkCount : std_logic_vector (3 downto 0) := "0000"; --counter for input clock signal clkCount : std_logic_vector (9 downto 0) := "0000000000"; --counter for input clock signal outTick : std_logic := '0'; --constant clk_check : std_logic_vector := "1010"; constant clk_check : std_logic_vector := "1111101000"; begin process(CLK_IN) begin if CLK_IN'Event and CLK_IN = '1' then if(clkCount = clk_check) then outTick <= '1'; clkCount <= "0000000000"; else outTick <= '0'; clkCount <= clkCount + 1; end if; end if; end process; CLK_OUT <= outTick; end Behavioral;
  11. I read on the Anvyl reference manual that the spartan 6 chip is capable of 500MHz clock speeds, but all the demos seem to be based off of 100MHz. Is this because it's using the on-board crystal oscillator, or is it because of the speed setting in the project properties?