Michael Harpe

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  1. Which files do you want? I tried to upload the project archive but this site complained that it was too large.
  2. Thanks. Also, getting the design to implement was interesting. I have quite a time getting the property CFGVBS set properly. I finally found the right screen to set it and it ended up in my constraints file at the bottom. I already had it at the top so I learned that order counts :-). I freely admit that I am new to the FPGA world and Vivado. Thanks for passing on my request.
  3. I am working with the Block Design flow in Vivado 2015.3. I don't seem to be getting how to connect the reset system. My design keeps acting like the clock is being held in reset. When I look closely it appears that the reset signal on the Arty is active low while the reset module in the design expects active high. What am I missing here? Michael Harpe
  4. Got it! Looks good. Thank you.
  5. I can confirm the problem with the Arty board definition being incorrect. I posted about this over at Avnet but there has been no response. I bought my board from them. I am attaching the ZIP file that I loaded into Vivado per the instructions. This is a pain because it's hard to get a MicroBlaze design going with an error like that. Any help is appreciated. Mike Harpe N4PLE arty.zip