José Enrique

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  1. Hi, Finally the 3,3V from the I/O doesn't shoot the mosfets.. I try with the 5V from a pin 5V0 of the artixA7 and two mosfets are shooted. In my circuit the current through the Drain are 0.165A in Sa1, 0.09A in Sa2 and 0.024 in Sa3. With 5V Sa2 and Sa3 works fine, but Sa1 nothing. Tomorrow i'll buy resistors to tray to reduce the current. I have 8V on the source and a little resistor of 50 ohms like the load, I'll try with 500 ohms or something like that to achieve shooting the mosfets. Gate-Source Threshold Voltage VGS(th) _____________VDS = VGS, ID = 250 μA __________1.0 - 2.0 V these are the parameters of the mosfet which I use, they say from 1 to 2V with a drain current 250uA, I have to reduce it in my circuit.
  2. hi @zygot, I think like you, every person learns more solving problems... I'll see the mistakes in the old code compare it with the new one to know the differences, today i have no time to see that today because I want to give my project to the university on July 6th and I am short on time... I did two courses about FPGA and VHDL on Udemy, and I want to do more about this topic, I like it a lot, If you can suggest me some book or online course I'll be very greatfull. You are certain and my design don't works fine, the multilevel inverter should have 7 levels of different voltages from +8V to -8V, but only it has 3 levels (+1V, 0V, -1V). I think that could be that no all mosfet are shooted... These are the mosfet https://www.mouser.es/ProductDetail/844-IRL530PBF , it is a special type of mosfet which is used with microcontrollers and fpgas because only needs 1-2V to be shooted. I put a 3.3k ohm resistor to connec the gate of Mosfet to the output of the FPGA pmod following the suggestion of this page https://www.inventable.eu/como-conectar-un-mosfet-a-un-microcontrolador/ but it didn't work. I need to review more information of mosfet to achieve that it works fine. I am learning a lot with this part of my project about power electronics and FPGA, much more than in my degree of electronics, I am happy with it. Thanks for your help zygot
  3. hi, this is my new code... I made some changes with your suggestions and now every output work fine, great!!! I only have 1 warning, I think that the problem was the 'if' sentence and the mixed types, as you told me. This weekend I'll connect again the fpga board to the protoboard with the Mosfets. In my universtitary studies we never did any circuit like this but in my project I did simulations of Inverters, Rectifiers and AC/AC and DC/DC converters on Matlab Simulink using Mosfets and Thyrestors. As the last point I wanted to do a circuit of some of this devices, I think that I could do it, hahah, I am going step by step, achieveing little goals, I hope that it works. This weekend I'll tell you something... very greatfull for your help library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity CONT is port ( CLK, a_Reset, enable : in std_logic; Sa1, Sa2, Sa3, Sa1n, Sa2n, Sa3n : out std_logic; Sb1, Sb2, Sb3, Sb1n, Sb2n, Sb3n : out std_logic); end CONT; architecture ESTRUCTURA of CONT is -- señales y constantes -- contador signal contador : std_logic_vector (17 downto 0) := (others => '0'); constant max_val : std_logic_vector (17 downto 0) := "111101000010010000"; -- salidas signal Sa1_out, Sa2_out, Sa3_out : std_logic := '0'; signal Sb1_out, Sb2_out, Sb3_out : std_logic := '0'; begin -- contador 250.000 * 10ns = 2.5ms = 1/400 Hz proceso_contador : process (CLK, a_Reset, enable, contador) begin if a_Reset = '1' then contador <= (others => '0'); elsif rising_edge(CLK) then if ((contador = max_val) or (enable = '0')) then contador <= (others => '0'); else contador <= contador + 1; end if; end if; end process proceso_contador; -- activo salidas para convertir onda a senoidal proceso_salidas : process (contador) begin case contador is when "000010111010111000" => Sa3_out <= '1'; when "000101110101111010" => Sa2_out <= '1'; when "001000110000101000" => Sa1_out <= '1'; when "010101110000100000" => Sa1_out <= '0'; when "011000101011011000" => Sa2_out <= '0'; when "011011100110000110" => Sa3_out <= '0'; when "100001011100000000" => Sb3_out <= '1'; when "100100010111000010" => Sb2_out <= '1'; when "100111010001110000" => Sb1_out <= '1'; when "110100010001101000" => Sb1_out <= '0'; when "110111001100100000" => Sb2_out <= '0'; when "111010000111001110" => Sb3_out <= '0'; when others => null ; end case; end process proceso_salidas; Sa3 <= Sa3_out; Sa2 <= Sa2_out; Sa1 <= Sa1_out; Sb3 <= Sb3_out; Sb2 <= Sb2_out; Sb1 <= Sb1_out; -- inversion de salidas complementarias Sa1n <= not Sa1_out; Sa2n <= not Sa2_out; Sa3n <= not Sa3_out; Sb1n <= not Sb1_out; Sb2n <= not Sb2_out; Sb3n <= not Sb3_out; end ESTRUCTURA;
  4. finally it works ,thanks Bianca for your help. I installed a tools and it works...
  5. these are the warnings, surely the problem are related in these warnings, tomorrow I'll see deeply these massages. Today I am a little bit tired, i worked all day. Thanks for your help and suggestions zygot. synthesis (7 warnings): [Synth 8-327] inferring latch for variable 'Sa1_out_reg' ["C:/Users/jesvk/OneDrive/Escritorio/TfG/VHDL new/INV_MULTI/INV_MULTI.srcs/sources_1/new/CONT.vhd":71](5 more like this) [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Implementation (7 warnings) Pin Planning: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. Phisical configuration: [DRC PDRC-153] Gated clock check: Net Sa1_out_reg_i_1_n_0 is a gated clock net sourced by a combinational pin Sa1_out_reg_i_1/O, cell Sa1_out_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
  6. hi zygot, the last times I try with nothing connected to the Arty board, I've measured with an oscilloscope the outputs of pmods. With the first configuration of constranints only it works 4 outputs of each pmod and when I try with the second one it works 6 outputs of pmodJD and 4 of pmodJA. In my multilevel inverter desing I use 12 low level MOSFETs, which I can shoot with a voltage like 2V, and I have 3.3 in the outputs of pmods. I am sure that I am in a some kind of mistake, I have to find it, hahahah. Iam a newbie in this field, but I want to develop my career with FPGA, It was the most interesting subject for me, of my degree. I have to work hard and learn, hahah I did a simulation, and all outputs works like I want... but surely I don't see something.. this is the simulation code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity Test_CONT is end Test_CONT; architecture ESTIMULOS of Test_CONT is component CONT port ( CLK, a_Reset, enable : in std_logic); end component; -- señales y constantes signal a_Reset, enable, CLK : std_logic; begin DUT : CONT port map (CLK, a_Reset, enable); -- contador 250.000 * 10ns = 2.5ms = 1/400 Hz RELOJ: process begin CLK <= '1'; wait for 5 ns; CLK <= '0'; wait for 5 ns; end process RELOJ; VALORES : process begin a_Reset <= '1'; enable <= '1'; wait for 20 ns; a_Reset <= '0'; wait for 40 ns; enable <= '0'; wait for 20 ns; enable <= '1'; wait for 90 ns; enable <= '0'; wait for 40 ns; enable <= '1'; wait; end process VALORES; end ESTIMULOS;
  7. This is the vhdl to a part of my finnal assigment of my engineering... I want to give to the university on the first week of July... I have to do it, hahah. It is a simple counter, but I have to make it works with the mosfet of the protoboard... some idea of the possible issues? thanks for help library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity CONT is port ( CLK, a_Reset, enable : in std_logic; Sa1, Sa2, Sa3, Sa1n, Sa2n, Sa3n : out std_logic; Sb1, Sb2, Sb3, Sb1n, Sb2n, Sb3n : out std_logic); end CONT; architecture ESTRUCTURA of CONT is -- señales y constantes -- contador signal contador : std_logic_vector (17 downto 0) := (others => '0'); constant max_val : integer := 250000; -- salidas signal Sa1_out, Sa2_out, Sa3_out : std_logic := '0'; signal Sb1_out, Sb2_out, Sb3_out : std_logic := '0'; begin -- contador 250.000 * 10ns = 2.5ms = 1/400 Hz proceso_contador : process (CLK, a_Reset, enable, contador) begin if a_reset = '1' or (contador = max_val) or enable = '0' then contador <= (others =>'0'); elsif rising_edge (CLK) then contador <= contador + 1; end if; end process proceso_contador; -- activo salidas para convertir onda a senoidal proceso_salidas : process (CLK, contador) begin case contador is when "000010111010111000" => Sa3_out <= '1'; when "000101110101111010" => Sa2_out <= '1'; when "001000110000101000" => Sa1_out <= '1'; when "010101110000100000" => Sa1_out <= '0'; when "011000101011011000" => Sa2_out <= '0'; when "011011100110000110" => Sa3_out <= '0'; when "100001011100000000" => Sb3_out <= '1'; when "100100010111000010" => Sb2_out <= '1'; when "100111010001110000" => Sb1_out <= '1'; when "110100010001101000" => Sb1_out <= '0'; when "110111001100100000" => Sb2_out <= '0'; when "111010000111001110" => Sb3_out <= '0'; when others => end case; end process proceso_salidas; Sa3 <= Sa3_out; Sa2 <= Sa2_out; Sa1 <= Sa1_out; Sb3 <= Sb3_out; Sb2 <= Sb2_out; Sb1 <= Sb1_out; -- inversion de salidas complementarias Sa1n <= not Sa1_out; Sa2n <= not Sa2_out; Sa3n <= not Sa3_out; Sb1n <= not Sb1_out; Sb2n <= not Sb2_out; Sb3n <= not Sb3_out; end ESTRUCTURA; -------------------------------- with this constraints i am not able to achive the Sa3 and Sa3n put their output in '1'... the other outputs work fine in their time... ## Pmod Header JA #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0]}]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { Sa2n }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { Sa1n }]; #IO_L6N_T0_VREF_15 Sch=ja[7] #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { Sa2 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { Sa1 }]; #IO_25_15 Sch=ja[10] ## Pmod Header JD set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { Sb3n }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { Sb2n }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { Sb1n }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { Sb3 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { Sb2 }]; #IO_L15P_T2_DQS_35 Sch=jd[9] set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { Sb1 }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
  8. yes, I was trying without anything connected to the board, it's very strange... it's like with the vhdl code for the multilevel inverter some pins of each pmod couldn't be connected at the same time, becouse I try with this new code and constraint and all of 16 pins are working at the same time: entity pmod is Port ( enableJA, enableJD : in STD_LOGIC; PinJA, PinJD : out std_logic_vector(7 downto 0)); end pmod; architecture Behavioral of pmod is begin PinJA <= "11111111" when enableJA = '1' else (others => '0'); PinJD <= "11111111" when enableJD = '1' else (others => '0'); end Behavioral; constraint file: ## Switches set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { enableJD }]; #IO_L12N_T1_MRCC_16 Sch=sw[0] #set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1] #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2] set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { enableJA }]; #IO_L14P_T2_SRCC_16 Sch=sw[3] # Pmod Header JA set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { PinJA[0] }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { PinJA[1] }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { PinJA[2] }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { PinJA[3] }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { PinJA[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { PinJA[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { PinJA[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { PinJA[7] }]; #IO_25_15 Sch=ja[10] ## Pmod Header JD set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { PinJD[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { PinJD[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PinJD[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { PinJD[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { PinJD[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { PinJD[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { PinJD[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9] set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { PinJD[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
  9. hi zygot, thanks for your help I am using the fpga board only to shoot the Gate of 12 low power mosfet. This mosfet works as an interruptor, the maximun voltage that cross from Drain to Source in each mosfet is 8V, it is a low level circuit to convert 8V DC to a +- 8AC. I check the I/O pin at the board with an oscilloscope. I did a simulation in vivado and all outputs are activated. I did a counter from 0 to 250000 to create a signal with 2.5ms of period, when the counter is in a particular number of the count a I/O pin is activated or deactivated. Maybe I am not explain very good the situation, my english is more or less, hahaha. This is the constraint configuaration of pmodJD, I don't change nothing in it in the two tests. But in the first test only works 4 and in the second one, it works 6. It is a strange situation: ## Pmod Header JD set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { Sb3n }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { Sb2n }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { Sb1n }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { Sb3 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { Sb2 }]; #IO_L15P_T2_DQS_35 Sch=jd[9] set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { Sb1 }]; #IO_L15N_T2_DQS_35 Sch=jd[10] But in pmodJA, I try in two ways: Firstly I did this configuration, and only works Sa1, Sa2, Sa1n, Sa2n, Sb1, Sb2, Sb1n and Sb2n. ## Pmod Header JA set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { Sa2n }]; #IO_L4P_T0_15 Sch=ja[2] #set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_L4N_T0_15 Sch=ja[3] #set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { Sa1n }]; #IO_L6N_T0_VREF_15 Sch=ja[7] set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { Sa2 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { Sa1 }]; #IO_25_15 Sch=ja[10] Then I changed the pins of Sa3 and Sa3n, to try a new way... and then it works Sa1, Sa2, Sa1n, Sa2n, Sb1, Sb2, Sb3, Sb1n, Sb2n and Sb3n. With this new configuration Sb3 and Sb3n works, but Sa3 and Sa3n doesn't work yet. ## Pmod Header JA #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { Sa2n }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { Sa1n }]; #IO_L6N_T0_VREF_15 Sch=ja[7] #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { Sa2 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { Sa1 }]; #IO_25_15 Sch=ja[10]
  10. hi, someone have any idea to help me... thanks I am trying to do an multilevel inverter with low power mosfet but i can't achieve that all of the I/O ports of pmod A and D works. I am using 6 ports in each pmod but i only could activate 4 in each, then i changed two constraits which didn't work, in pmodA and then the 6 ports in pmod D work fine, but i can't achive activate this two I/O in pmodA. This is the configuration after change the two ports in pmod A. I don't know if it is better to use only 3 ports in each pmod or I can use 6 ports in each, becouse now 6 ports works fine y pmodD but only works 4 in pmodA, and I need 12 ports to my proyect. ## Pmod Header JA #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { Sa2n }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { Sa3n }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { Sa1n }]; #IO_L6N_T0_VREF_15 Sch=ja[7] #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { Sa3 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { Sa2 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { Sa1 }]; #IO_25_15 Sch=ja[10] ## Pmod Header JD set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { Sb3n }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { Sb2n }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { Sb1n }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { Sb3 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { Sb2 }]; #IO_L15P_T2_DQS_35 Sch=jd[9] set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { Sb1 }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
  11. hello, i have the same problem... my laptop can't see the board even it doesn't appear in the ports com section when I connect it... I try to reinstall the drivers but I can't do it because windows tells that i am not an admin... someone have any idea to fix it? I try with different USB cables but I think that I need the drivers or my Arty A7 doesn't work fine...