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About ASMartin

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    : Malaga (Spain)

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  1. Hi. Still waiting for a new stereo cam system, maybe for FMC interface to use with Nexys Video. Any new?
  2. Hi guys, I'm Alex from spain, working on Stereovision project to see depth of objects using VmodCAM and Atlys. But I never sent my project to anybody. Regards, Alex
  3. Hi virtextoo, Thanks for you reply. I asked to Bianca and seems to be a long term project (some months, at least), so by now, we have to keep using VmodCAM with this adapter for Nexys Video. Regards, ASMartin
  4. Hello Bianca, Any new about the new stereo cam system?, no information regarding this issue in the "New Products" or "Coming Soon" menues from main page. Kind Regards from Spain
  5. My personal library also includes: FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version by Chu
  6. Thanks Virtextoo. I'm a man of facts rather than promises . I previously asked for a stereovision camera module like VmodCAM for Nexys Video (FMC-LPC interface) last october, but I received no answer. That's why I decided to develop this interface adapter.
  7. Hello Bianca, I developed an interface card or adapter to connect VmodCAM to FMC-LPC interface (mainly Nexys Video oriented). You can have a view in this subforum, VmodCAM2FMC Interface Card Maybe this could be interesteing for VmodCAM users to migrate to Nexys Video. Best Regards.
  8. ASMartin

    Nexys Video + Camera

    Hi Jay, I finally mounted and FMC-LPC to VHDCI adapter to connect the VmodCAM module to the Nexys Video. It looks like this: It's just a prototype. I also developed a UCF (.ucf) file to map VmodCAM signals to Nexys Video FMC port. Maybe this could help you.
  9. Hi ALL!!! I made an adapter to connect VmodCAM to Digilent Nexys Video FPGA board through the FMC connector. It looks like this: Top View (VHDCI Connector) Bottom View (FMC-LPC Connector) VHDCI Connector View VmodCAM (Not included) VHDCI Male to Male Cable (Not included) Digilent Nexys Video (Not included) Please note the VHDCI connector is female so you will need a VHDCI male to male cable to connect the VmodCAM (not straight connection). This is a prototype so if you are interested just contact me. Attached file is a User Constraints File (.ucf) for this module on Digilent Nexys Video. Just to wish you Merry Christmas !!! nexys_video_vmodcam.ucf
  10. Well, 33 is not allowed (greater than 32) but I will try these ratio converters: x11/16 to give 68.75 MHz (with a VCO working at 1100 MHz) and x27/25 to give 74.25 MHz (with an VOC working at 1856.25 MHz). Thanks for your help, mate.
  11. Hi Mike, Thanks for your solution but range is now working, CLKFX_DIVIDE in range (1 to 256) CLKFX_MULTIPLY in range (2 to 256) for DCM_CLKGEN, but for DCM_SP CLKFX_DIVIDE in range (1 to 32) CLKFX_MULTIPLY in range (2 to 32) So it's not possible to synthesize 33Mhz I need to obtain 74.25 MHz. The trouble is just the warning message.
  12. Hi Sam, thanks a lot for your support and information. I've to use DCM_CLKGEN because I need a 33/100 ratio and I can't obtain that clock ratio with a DCM_SP (out of range). So I will suffer this warnings
  13. Hi. I need some help about ISE Xillinx. I used a combined DCM-CLKGEN (master) and a DCM_SP (slave) clock generators to obtain 75.25 MHZ for HD (720p) HDMI output at 60Hz. This is the code: TMDS_MASTER_DCM: DCM_CLKGEN generic map ( CLKFXDV_DIVIDE => 2, -- CLKFXDV divide value (2, 4, 8, 16, 32) CLKFX_DIVIDE => 100, -- Divide value - D - (1-256) CLKFX_MULTIPLY => 33, -- Multiply value - M - (2-256) SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE" STARTUP_WAIT => FALSE, -- Delay config DONE until DCM_CLKGEN LOCKED CLKIN_PERIOD => 10.000, -- Input clock period specified in ns CLKFX_MD_MAX => 0.000 -- Maximum M/D ratio for timing anlysis ) port map ( -- Input clock CLKIN => mclk, -- Input clock (100MHz Master Clock) -- Output clocks CLKFX => clkfx_master, -- Generated clock output (33MHz) CLKFX180 => open, -- Generated clock output 180ยบ phase shift CLKFXDV => open, -- Divided clock output -- Ports for dynamic phase shift PROGCLK => '0', -- Clock input for M/D reconfiguration PROGEN => '0', -- Active HIGH program enable PROGDATA => '0', -- Serial data input for M/D reconfiguration PROGDONE => open, -- Successful re-programming (active HIGH) -- Other control and status signals FREEZEDCM => '0', LOCKED => lock_master, -- Locked output STATUS => open, -- DCM_CLKGEN status RST => reset -- Reset input pin ); TMDS_MASTER_BUFG : BUFG port map ( O => clkfx_master_buf, I => clkfx_master ); ---- Slave DCM Configuration ---- ---- Output Output Phase Duty Pk-to-Pk Phase ---- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps) ---- ------------------------------------------------------------------------ ---- clkfx_slave 74.250 0.000 50.0 469.360 150.000 ---- ---- ---- Input Clock Freq (MHz) Input Jitter (UI) ---- ----------------------------------------------------- ---- clkfx_master_buf 33.000 0 .010 TMDS_SLAVE_DCM: DCM_SP generic map ( CLKDV_DIVIDE => 2.000, -- CLKDV divide value CLKFX_DIVIDE => 4, -- Divide value CLKFX outputs CLKFX_MULTIPLY => 9, -- Multiply value CLKFX outputs CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two -- CLKIN_PERIOD => 30.303, -- Input clock period (ns) CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift CLK_FEEDBACK => "1x", -- Feedback source DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS DFS_FREQUENCY_MODE => "LOW", -- Unsupported DLL_FREQUENCY_MODE => "LOW", -- Unsupported DSS_MODE => "NONE", -- Unsupported DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported FACTORY_JF => X"c080", -- Unsupported PHASE_SHIFT => 0, -- Amount of fixed phase shift STARTUP_WAIT => FALSE -- Delay config DONE til LOCKED ) port map ( -- Input clock CLKIN => clkfx_master_buf, -- Clock input CLKFB => '0', -- Clock feedback input -- Output clocks CLK0 => open, -- 0 degree clock output CLK90 => open, -- 90 degree clock output CLK180 => open, -- 180 degree clock output CLK270 => open, -- 270 degree clock output CLK2X => open, -- 2X clock frequency output CLK2X180 => open, -- 2X clock frequency, 180 degree CLKFX => clkfx_slave, -- Digital Frequency Synthesizer CLKFX180 => open, -- 180 degree CLKFX output CLKDV => open, -- Divided clock output -- Ports for dynamic phase shift PSCLK => '0', -- Phase shift clock input PSEN => '0', -- Phase shift enable PSINCDEC => '0', -- Phase shift increment/decrement PSDONE => open, -- Phase shift done output -- Other control and status signals LOCKED => lock_slave, -- DCM_SP Lock Output STATUS => open, -- DCM_SP status output RST => reset_slave, -- Active high reset input -- Unused pin, tie low DSSEN => '0' -- Specify to GND ); TMDS_SLAVE_BUFG : BUFG port map ( O => clkfx_slave_buf, I => clkfx_slave );And I obtain the following message when mapping: I would like to avoid this warning, but I can't find the trouble. Indeed DCM_CLKGEN does not define any attribute regarding DFS_OSCILLATOR_MODE. Thanks in advance.
  14. Yeap, that's the right solution, the one provided with DDR2 for 6 family by MIG. I have to implement 3 queues with FIFOs and a round-robin mechanism to access them. I know, but I'm looking for a working solution to save time. I've been working with ATLYS (Spartan 6) with vmodcam and HDMI output (HD720p split) and some algorithms to enhance borders and color mapping just for a stereovision system, but I need more slices I already designed and implemented a card to interface FMC to VHDCI (VmodCAM interface). And I'm now mapping the example for VmodCAM from Atlys to Nexys Video, just for testing purposes (I need to sve time just for testing). But IP core for 7 family is quite different and does not provide with 3 ports I need. I translated buffers, clock manager and so on, but memory interface is different. Thanks a lot for your support. Regards.