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kringg last won the day on May 12

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  1. For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog.
  2. @[email protected], Your suggestion of examining my clock domain crossings was spot-on. Thank you! There was a bug in the FIFO queue I was using to cross from system-clock-space to sdram-clock-space. Once I fixed that, everything fell into place. I'll post the final working code in a bit; I found this to be a very challenge problem due to lack of good MIG User Interface examples, so hopefully my heartburn can help someone else. @tom21091, Thanks for the simulation model, that'll be extremely helpful as I now integrate this subsystem into my larger project!
  3. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code,