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  1. @[email protected] @zygot I decided to go forward with your recommendation on using the DataMover. So now I have my custom module and the DataMover IP in my BD. I tried to make a basic test of the DataMover, where in my custom HDL I write a magic 32-bit number every clock cycle to the AXI-Stream line going to DataMover S2MM. There is also a 72-bit AXI-Stream Command interface to the DataMover, where I put the address in DDR I'd like to write to, per PG022. I also assigned constants to the other fields, mostly all 0, and put 4 for BTT because for the test I want to set a 32-bit area of memory. Don't see any indication that it's writing it when I read that location from software. Have I messed up the AXI protocol by doing these writes every clock cycle? I feel like its something to do with valid, ready, last, and all the other wires I'm not too clear on. Additionally, the Vivado connection automation connected DataMover's output S2MM to the AXI Interconnect IP. Is that right, and it should still be able to reach DDR? Edit: I was thinking about other reasons for it not working. I do disable data cache in SW. I think since I'm running baremetal it should be ok to copy and paste a hardcoded pointer from SW into Vivado to use for the SADDR of the AXI-Stream Command? No odd virtual address translation going on?
  2. Thanks for y'all's responses! I got my VHDL code working as an RTL module now, definitely needed to use the IP Packager to at least create the stubs for all the AXI ports and registers I needed. Now I'm thinking about the DMA part. @zygot You mentioned a few options, I definitely want the data to be available in PS DDR, not BRAM. I was reading about the Data FIFO and Virtual FIFO. Can you elaborate on "you can connect one side to an AXI DMA controller. The slave side is made external." for the Data FIFO? Are you saying it would look like MyCustomBlock --> Data FIFO --> AXI DMA Controller --> DDR? Also I (might be wrong) understand the Virtual FIFO differs because it's making use of external memory like the DDR for the FIFO's data itself. Wouldn't this eliminate the need for a DMA block altogether? But how would I configure it to use a fixed address that I also need to read in PS? Also, it being a FIFO, won't I run into problems when I want to overwrite the DDR block with fresh data-- nobody is "popping" from the FIFO in the usual sense. Could I just put it in reset then write the fresh data and it restarts at the original DDR location? Furthermore, with your help I'm understanding the way this is all hooking together at a high level pretty well! Actually implementing the interface from my custom block to the FIFO without using PS drivers is still daunting to me, though. What would the interface need to be on the BD? Right now my custom block has a master AXI interface, but can I connect this to the FIFO, or do I have to go through the Interconnect? All in all it's a fun learning process for a software guy like me
  3. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
  4. Hi all, You know how when you first power on the board, the LEDs cycle in a pattern and the HDMI TX displays a rainbow test pattern? I was wondering if the sources/a Vivado project for that behavior exists somewhere, it would be cool to see how all that is done. Thanks!