itse me mario

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  1. I had an error in an old file (fsm_fir_get_data)... Now DA_SDIN, etc represent the data. ... begin calc_next_state: process ( state,start_fs_tic_f ) begin case state is --************new**************** when s_idle => if (start_fs_tic_f='1') then nxt_state <= s_read; end if; --****************************** --************old*************** when s_idle => if (start_fs_tic_f='1' AND rising_edge(start_fs_tic_f) ) then nxt_state <= s_read; end if; --***************************** ...
  2. I´m running out of ideas... Testbench works fine. Using the analog discovery 2 I can measure the clock signals (MCLK, LRCK, SCLK). AD_SDOUT and DA_SDIN remain 0 (see AD2_neu2.png). Using the ILA (when AD2 is also connected) all signals remain zero. Without AD2 it shows at least values for audio_l_out and audio_r_out. AD_SDOUT also seems to work. I also tried once with set_property CONFIG_VOLTAGE 5 [current_design] but it did not help. My XDC: set_clock_groups -asynchronous -group [get_clocks *clk_out1*] -group [get_clocks *clk_out2*] set_property CFGBVS
  3. In my testbench I started feeding AD_SDOUT one LRCK too late and this was the reason for my error.
  4. I just used constant values for s_filter_input_data_16_bit_l and s_filter_input_data_16_bit_r (x"00FF") and the problem for a_sop disappears. What is the reason for this? :D
  5. The RTL of the FIR-Filter is shown in RTLFIRFilter.png. Instead of s_fs_tic_16_kHz and s_fs_tic_16_kHz_delay I use the hphone_valid signal now. The process ctr_16 bit is also no longer needed.
  6. Hello together, as mentioned I bought the PMOD-I2S interface, so I don´t need an I2C master controller anymore. I changed my design and added my previously designed FIR-Filter (see RTL.png). I use a MCLK of 8.192 MHz, a LRCK of 32 kHz and a SCLK of 2.048 MHz. My filter needs 16 bit input data and creates 16 bit output data. Unfortunately in my new design in the beginning every second value in array a_sop (Array of Sum of Products) is XXXX...XXXX and I don´t know why. I tried different things, but nothing works so far (see WrongValues, WrongValues_zoom, WrongVal
  7. Hello again. I just came over something very interesting: https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ With that I don´t need the codec configuration with I2C and I only have to do the I2S-Interface. I´m going to order this and I hope this will work as exptected for me.
  8. Does anyone have an idea, where I can get help for my problem? Unfortunately, I haven't made any progress for a long time...
  9. Hello it´s me again. Another problem occured. When using the ILA, I get a warning (see attachment). When I use an already tested program on the Genesys2, I get the same error message, but the ILA shows the right results and triggers. Could this warning be the reason why it´s not working, or does it not affect the functionality? My ILA clock is directly connected to the output from the clocking wizard. The following link https://www.xilinx.com/support/answers/64764.html hasn´t helped me so far. As trigger signals I used new_sample=1 and the rising edge of sample_clk_48k. Unfortunately the
  10. Some updates. Took a while because I tried out a lot. I set the 48 MHz and 100 MHz clocks from the clocking wizards output to be asynchronous (https://www.xilinx.com/video/hardware/clock-group-constraints.html). Now in the XDC I have: set_clock_groups -asynchronous -group [get_clocks *clk_out1*] -group [get_clocks *clk_out2*]. I also added set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] in the XDC. Furthermore I added additional board files (https://reference.digilentinc.com/reference/software/vivado/board-files). Unfortu
  11. Ok I can only upload 2MB. I have to wait... I will try to implement the design with a lower clock rate. Maybe the timing problems will disappear.
  12. I attached the new module overview and block design. Furthermore I attached my timing error. Right now, I don´t see what´s wrong. Modules_BlockDesign_reducedsize.pdf
  13. Updated some files. Added the ADAU1761_interface from the former Design from Stefan Scholl and therefore deleted my clk_24_MHz signal in some modules. clocking.vhd reg_pack.vhd i3c2.vhd adau1761_configuraiton_data.vhd i2c.vhd i2s_data_interface.vhd ADAU1761_interface.vhd audio_testbench.vhd ADAU1761_izedboard.vhd audio_top.vhd
  14. Hi, thanks again for your answer! >>break down the problem into smaller pieces I think so, too. Otherwise it´s hard to find the errors. >>BTW, the current consumption of your codec might serve as quick-and-dirty indicator that your register writes are going through (works for a module, not sure if this will help you).. Alright this might be a good idea, thank you! >>PS: "FPGA" is DSP implementation, [...] Yes I first developed the algorithm on a DSP and a microcontroller and checked the transfer function. I additionally checked and
  15. Hi, thank you for your answer. Okay I will try to solve this timing problem first, before I continue. I already worked on some projects (7 segment decoder, UART with AXI: register reader, FIR filter, ILA in a small project), also with state machines. I have problems with the audio codec, but the framework, especially the state machines for the initialization should actually work. Maybe I added some errors... One thing is that I really need a working audio codec for my future projects (FIR filter and adaptive filter next). >>For example, a small state machine t