itse me mario

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  1. Hello again. I just came over something very interesting: https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ With that I don´t need the codec configuration with I2C and I only have to do the I2S-Interface. I´m going to order this and I hope this will work as exptected for me.
  2. Does anyone have an idea, where I can get help for my problem? Unfortunately, I haven't made any progress for a long time...
  3. Hello it´s me again. Another problem occured. When using the ILA, I get a warning (see attachment). When I use an already tested program on the Genesys2, I get the same error message, but the ILA shows the right results and triggers. Could this warning be the reason why it´s not working, or does it not affect the functionality? My ILA clock is directly connected to the output from the clocking wizard. The following link https://www.xilinx.com/support/answers/64764.html hasn´t helped me so far. As trigger signals I used new_sample=1 and the rising edge of sample_clk_48k. Unfortunately the
  4. Some updates. Took a while because I tried out a lot. I set the 48 MHz and 100 MHz clocks from the clocking wizards output to be asynchronous (https://www.xilinx.com/video/hardware/clock-group-constraints.html). Now in the XDC I have: set_clock_groups -asynchronous -group [get_clocks *clk_out1*] -group [get_clocks *clk_out2*]. I also added set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] in the XDC. Furthermore I added additional board files (https://reference.digilentinc.com/reference/software/vivado/board-files). Unfortu
  5. Ok I can only upload 2MB. I have to wait... I will try to implement the design with a lower clock rate. Maybe the timing problems will disappear.
  6. I attached the new module overview and block design. Furthermore I attached my timing error. Right now, I don´t see what´s wrong. Modules_BlockDesign_reducedsize.pdf
  7. Updated some files. Added the ADAU1761_interface from the former Design from Stefan Scholl and therefore deleted my clk_24_MHz signal in some modules. clocking.vhd reg_pack.vhd i3c2.vhd adau1761_configuraiton_data.vhd i2c.vhd i2s_data_interface.vhd ADAU1761_interface.vhd audio_testbench.vhd ADAU1761_izedboard.vhd audio_top.vhd
  8. Hi, thanks again for your answer! >>break down the problem into smaller pieces I think so, too. Otherwise it´s hard to find the errors. >>BTW, the current consumption of your codec might serve as quick-and-dirty indicator that your register writes are going through (works for a module, not sure if this will help you).. Alright this might be a good idea, thank you! >>PS: "FPGA" is DSP implementation, [...] Yes I first developed the algorithm on a DSP and a microcontroller and checked the transfer function. I additionally checked and
  9. Hi, thank you for your answer. Okay I will try to solve this timing problem first, before I continue. I already worked on some projects (7 segment decoder, UART with AXI: register reader, FIR filter, ILA in a small project), also with state machines. I have problems with the audio codec, but the framework, especially the state machines for the initialization should actually work. Maybe I added some errors... One thing is that I really need a working audio codec for my future projects (FIR filter and adaptive filter next). >>For example, a small state machine t
  10. Hello everybody, I´m trying to implement a FIR filter with a sampling rate of 16 kHz on the Genesys 2 Board (Vivado 2019.2, VHDL). For that reason I need to configure the onboard Audio-Codec (ADAU1761). I already designed a FIR-filter, that I want to use later. Unfortunately I am quite new to FPGA design and I´m struggling a bit with it. I found an article „Audio Interface for the Zedboard“ from Stefan Scholl (TU Kaiserslautern Germany, see https://kluedo.ub.uni-kl.de/frontdoor/deliver/index/docId/4034/file/zedboard_audio_doc.pdf), which is based on a framework from Mike Field alias
  11. During my master - which contents a lot of practical projects - I work in a laboratory on my own projects. There are also some fellow students in the lab (but they have different topics) , and I don´t know anyone (instead of one professor) that I can ask in FPGA specific topics. My supervising professor can help me in any other signal processing topic, but FPGAs.
  12. My name is Mario, I am in my 3rd (and hopefully last) master semester (electrical engineering) and I am a FPGA rookie. I don´t have too much experience in FPGA design and I´m looking forward to having some awesome, instructive and of course interesting conversations with you! I´m really interested in real-time signal processing, which is also the main topic of my master. Earlier in my master, I implemented filter algorithms on µC and DSP. I started implementing different FIR-filters a few months ago (on Nexys 4 DDR Board) and I´m now struggling on configuring the Genesys 2 audio codec. My tota