nkraemer

Members
  • Content Count

    4
  • Joined

  • Last visited

  1. Thanks for the detailed reply and good debugging tips zygot. I'm using a hybrid approach with some Xilix IP cores in the block diagram, and some custom RTL (including ethernet) communicating to the rest of the design over AXI. I was able to use the Verilog Ethernet open source project as a basis for the MAC plus some custom 'glue logic' to convert the axi stream bus to a memory mapped axi interface. While I have simulated basic behavior of the core, I admit I haven't thoroughly verified it. I am using Xilinx's IP and the board design flow for the QSPI, but I'm still getting errors abou
  2. Initially I was but I have switched to a custom MAC since the Etherniet-Lite core doesn't support all the features I want. I'm not certain that the bug is within the new MAC (it may be a firmware bug), but it would be nice to eliminate timing issues as a potential source of error.
  3. Thank you for the quick reply zygot. I'm currently tracking down an intermittent bug in my microblaze design and I want to be able to say with confidence that FPGA timing errors are not the source of the problem. Additionally, I believe it is good practice to have the tools guarantee that timing will be met on all communication buses. I would particularly like to avoid one FPGA build working, changing something unrelated, and then having a subsequent build fail because the tools weren't able to properly account for off-board timing constraints. I understand that certain pins like LEDs or switc
  4. I am working with an Arty design and I have noticed that while I have no intra-clock timing failures, I still have high severity warnings in the "check timing" portion of my timing summary related to not having constraints for input and output delay (no_input_delay and no_output_delay). Does digilent provide suggested timings for the on-board peripherals (like Ethernet and flash), or do I have to go through all the datasheets myself and estimate the trace delay? I found this thread from 2017, but the question was never resolved.