Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky.
Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation"
The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete.
The log gives the following in "Message:" (attached)
Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in case anyone wants to look at it.
Nexys 100T Blinky tutorial error generating Bitstream
in FPGA
Posted
Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky.
Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation"
The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete.
The log gives the following in "Message:" (attached)
Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in case anyone wants to look at it.
blinky.xpr Nexys-A7-100T-Master.xdc