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  1. Hello, (FPGA board is Nexys A7 100T) So my end goal is to implement RC4 stream cipher and implement it onto FPGA. I was trying to configure a switch that will utilize the 7-segment 8- digital display and display my original plain text. And another switch that will display the encrypted text. I have attached the sources and test benches below that works. And have screen captured the simulation to show the results. Thanks for spending the time, I'll be high alert for response and try to respond on follow up questions. Can someone help me with this?
  2. I fixed everything you have mentioned with the missing states and enlarged the dimensions. Quote: [ (what is now "2-to-4 decoder with active-low inputs" make it "3-to-4 decoder with active-low inputs".)] How would I make/ program a 3-to-4 decoder? When I thought a decoder is a circuit with n inputs and 2^2 outputs. Do you mean make a 3-to-8 decoder? I have attached how I have changed my "serializer.vhd" code. How do I appraoch the 3-to-4 decoder? (I really appreciate everyone's help!)
  3. I'm sorry, I've looked over the manual many times. But I'm not really understanding how I can modify how digits are being cycled. Is it possible for me to see how the code in "serializer.vhd" is adjusted? Also does anything else gets adjusted or just the serialize.vhd? Would there then be four more states? S1, S2.....S7? Thanks.
  4. Hello, I found a lot of open source and tutorials on how to build a 4 digit 7 segment display on the Nexys A7 board (or Nexys 4DDR). I was wondering how can I make all 8 digital displays light up and display a message in hexadecimals (ex: "85ECA921"). I'm doing this in xlinx vivado in VHDL code. I'll have attached of something that works for 4 digits, but can someone show me how to implement/ change the code to make all 8 digital displays work in that example I provided? Thanks serializer.xpr tb_serializer.vhd serializer.vhd my_genpulse.vhd hex2sev
  5. Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky. Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation" The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete. The log gives the following in "Message:" (attached) Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in ca
  6. HI! I had the same issue, but I followed exactly what kwilber did, but I still can not generate bitstream. This is what it says in my messages. Can anyone please help? I have it attached below.