tikitiki

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Posts posted by tikitiki

  1. Hi everyone

    i am using genesys2 board. I want to test the board with simple code.
    but i meet a problem with clock, can you help me to fix it? thank

    this is code:

     

    Quote

    `timescale 1ns / 1ps
    //////////////////////////////////////////////////////////////////////////////////
    // Company: 
    // Engineer: 
    // 
    // Create Date: 06/10/2015 12:33:28 PM
    // Design Name: 
    // Module Name: dram
    // Project Name: 
    // Target Devices: 
    // Tool Versions: 
    // Description: 
    // 
    // Dependencies: 
    // 
    // Revision:
    // Revision 0.01 - File Created
    // Additional Comments:
    // 
    //////////////////////////////////////////////////////////////////////////////////


    module test(
        input DIFF_SYS_P,
        input DIFF_SYS_N,
        output reg [7:0] led=8'd0,
        output clk
        );

        reg [31:0] count =0;
        wire clk;

        IBUFGDS #(
        .DIFF_TERM("FALSE"),
        .IBUF_LOW_PWR("TRUE"),
        .IOSTANDARD("DEFAULT")
        ) IBUFGDS_inst (
           .O(clk),
            .I(DIFF_SYS_P),
            .IB(DIFF_SYS_N)
            );


        [email protected](posedge clk) begin 
          if(count ==10) begin
            led <= 8'b10101010;
            count <=count +1;
           end

           else begin
           count<=count +1; 
         end
      end
    endmodule

    and this is xdc

    Quote

    #### This file is a general .xdc for the Genesys 2 Rev. H
    #### To use it in a project:
    #### - uncomment the lines corresponding to used pins
    #### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

    ## Clock Signal
    set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { DIFF_SYS_N }];  #IO_L12N_T1_MRCC_33 Sch=sysclk_n
    set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { DIFF_SYS_P }];  #IO_L12P_T1_MRCC_33 Sch=sysclk_p

    create_clock -period 5.000 -name DIFF_SYS_P -waveform {0.000 2.500} [get_ports DIFF_SYS_P]


    ## Buttons
    #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc
    #set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd
    #set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl
    #set_property -dict { PACKAGE_PIN C19   IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr
    #set_property -dict { PACKAGE_PIN B19   IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu
    #set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn

    ## LEDs
    set_property -dict { PACKAGE_PIN T28   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
    set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
    set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
    set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
    set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
    set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
    set_property -dict { PACKAGE_PIN W24   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
    set_property -dict { PACKAGE_PIN W23   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]

     the error in bitstream like this


    [DRC NSTD-1] Unspecified I/O Standard: 1 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk.
     

  2. thank [email protected]

    my point is that I already made a DRAM chip, so now I need to generate some commands like read, write; then give input data and check data ouput.
    I saw that some FPGA kits can generate square signals, but I dont know how about NEXYS4.
    because I see NEXYS4 has clock frequency is 100MHz, so i think it may generate some signals like data generator.