tuskiomi

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Everything posted by tuskiomi

  1. Hello all. I have for trade one Nvidia Jetson AGX Xavier development kit. It is a platform for energy efficient GPGPU applications. The thing is a titan of computations ,and It has had a good year with me. It runs a modified version of ubuntu linux, and is very fast. You can read more about it here: Read more. You can view images of the item here: images here. It is in mint condition, there is some damage to the processor JTAG header, which you can see on the right hand side. The pins are untouched, and my JTAG programmer still fits perfectly. I should note that I have never had
  2. tuskiomi

    basys 2 projects

    Oh, strange, I assumed that the xilinx logo on the 2 meant that vivado supported it... What software is used to design RTL code for the Basys 2?
  3. tuskiomi

    basys 2 projects

    Hello, I noticed in my 2019.2 installation of vivado that the Basys 2 is no longer selectable under the target boards window.. Can we still make projects for it?
  4. Good to see that I'm starting with the trivial implementation.
  5. Indeed, you are correct.
  6. Does digikey honor digilent academic discounts
  7. Okay, processor company jabbing aside ;-), I'd like to introduce my other application. Years ago I created a program which takes trained neural networks, and exports them to HDL -like formats (think lots of LUTs). Eventually, I'd like to take these neural networks, and if resources allow, place them directly into the fpga, which would allow a trained network to be executed in just a small number of clock cycles, instead of multiple hundreds. Trouble is, neural networks require lots of resources. One neuron will take up 8 LUT inputs, which is silly when you have thousands of neurons,
  8. I love this advice. In short the application is a generic RISC V core in which there are many smaller RISC CPUs which are simpler, and support much less instructions (no access to ctrl regs, half precision multiply, etc). i want to experiment with branch prediction, vector instructions, and simple loop compression, as well as what you mentioned with feeding algorithms. one step at a time though, and ive been modifying an open source risc V processor for the last few months, and at this point i cannot make any more progress without physical testing, as vivado doesnt support some vhdl 2008 featu
  9. Hello, I suppose I should have specified, I'm doing design involving high core counts (64+ cores), so it seems natural that i would run low on cells.
  10. Hello, all. I'm an aspiring CPU designer, looking to design my first CPUs, have compiler errors, and learn a lot along the way. I finished my first FPGA class this last semester, and I'm hungry for more. The FPGA we used in class was the Digilent Nexys A7. This board worked well for what we did in class, but I would like to upgrade, as I found myself commonly exceeding the number of cells available during experimentation. Here are my working requirements: Must have: At least one Ethernet port, either directly connected, or connected via PHY. Some sort of EEPROM or non
  11. Thank you, Can you speak as to if anything is in the works at a similar price point at this time? I may just hold out for something new if it's in the works, but if not, it's the Genesys 2.
  12. Hello, I'm looking to order a genesys 2 from the digilent store with an academic discount ASAP. Are there any ETAs of when they will be available?
  13. Hello, I may be seeing something incorrectly, but there are 1GB worth of RAM chips on the Genesys 2 board. The RAM is not included on the master XDC file. Is this a mistake, or is the ram coupled on a deeper level to where the XDC does not need to specify it?
  14. @JColvin I'll ask around on the Xilinx forum. There is an additional license for the webpack which is labelled "V_Webpack", I'm not sure what features that enables, but We'll find out soon. EDIT: The Webpack contains all of the features the the full edition of Vivado does, but it is limited to a select number of older FPGAs.
  15. Just to confirm, Does this include the licences outlined in red (which normally are free for 30 days, then require a one-time payment of 2,995$ to xilinx), or are they to be purchased separately?
  16. Hello. I'm looking for additional memory for my FPGA board. I looked at the schematic for the FMC on the Genesys 2 board, and found that it has enough IO to support a DDR/DDR2 SODIMM slot. Are there any products out there which can expand volatile memory through the FMC connectors? Any volatile memory is ok, but one for DDR or DDR2 RAM chips is preferred.
  17. Very interesting! do you know if there are Ram slots that connect to the FMC slot?
  18. Hello, I'm considering a Genesys 2 board for a communications FPGA. I see that on the schematic on page 17 that there is a chip by the part number of MT41J256M16HA-107, which is a 16x256MB ram chip. The package is a 96-TFBGA, however, when I look at the pictures of the front and the back of the board, there is no such chip anywhere. Is the chip underneath the heatsink, or is the chip elsewhere?