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  1. closer. Have reviewed the example main (used the 4.1 version). Got a response on my terminal application. Moved on to the 'xuartps_intr_example.c file, using it's main with the original Blinky app (and it's hardware config). Don't see any traffic at all over the uart with this example (I have made no changes - the posts I find online about ensuring 'XPAR_XUARTPS_0_INTR' and not 'XPAR_XUARTPS_1_INTR' were already present in the file in this example supplied with the 2019.2 Vitis. I do note (not sure it matters) that when I click on the Zynq block in the Vivado project that contained that was used for the Blinky example, the UART0 does not have a check next to it (however, that didn't seem to matter when data was sent from the xscugic_example file. Any ideas or pointers?
  2. Sometimes, all you need to do is post and then you find part of the answer! 🙂 Searching my computer for the header file scugic.h returned lots of instances, particularly an example using the V3.8 version of this driver. I chose the default directories when installing and I found this example at the following location. file:///C:/Xilinx/Vitis/2019.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scugic_v3_8/doc/html/api/xscugic__example_8c.html Last question in initial post still applies. Are there other options I should consider for interrupts?
  3. Hi All, I've been actively searching the forums here and over at Xilinx. Still working on some portions of my Zybo project and getting more capable with the Zynq processor and the FPGA capabilities. Sometimes, searches take me down rabbit holes and/or to dead-ends (part of the nature of fora, I guess). One thing in particular I'm trying to find more info on is useful ways/best practices for handling interrupts for the Zynq (want to setup interrupts for UART receive and then on some GPIO that the FPGA portion of the Zynq is also using). I've seen references to xscugic which seems to have been documented (somewhat?) in the old Xilinx SDK (which I can't find anywhere to download still). Is this interrupt framework/controller still useful and if so, can anyone point me to documentation (and perhaps a sample project)? Are there other options I should consider for interrupts? Peter
  4. Oh - I definitely have a space in the path name. I moved things to a new folder with no spaces anywhere in the path. That got me by the 'Next' button. I can continue the exercise. Much thanks for the help, JColvin!
  5. Hmmm... I think I have the same name as you've shown ('design_1_wrapper [custom]'). There is a space between the 'r' in wrapper and the text [custom] but I don' think that's different from what you showed. Interestingly, if I choose one of the already displayed choices - 'zed' for example - I can get by the 'Next' button. Perhaps trying the quick start all over again to see if I get any different result...
  6. Your second screen shot was very helpful. I see the same thing as on your first screenshot. I thin click 'Next' and I think Vitis tries to show the progress bar you've shown in the second picture. However, it happens so fast, I never really see the progress bar. Then I'm just put back to the first screenshot picture but the 'Next' button is greyed out. I found another post on this forum (I think from you!) that contained a Vitis IDE (zipped) for an arty_z7_20_base. I could open that in Vitis and look around with it. So in some ways, it seems Vitis is working. I just can't get by that first screen.
  7. Thanks for the link, JColvin. The process the link describes was exactly what I did (the initial example very helpful, obviously, and needed only a few tweaks as has been nicely done in the link you provided). The problem happens on step 7.4. when I click 'Next', Vitis hangs (well, 'hangs' isn't really the right word). Vitis does something (the dialog flashes for a moment) but then the 'Next' button becomes greyed out and I can't click it. I can click the back button and then I can try again, but each time the 'Next' button becomes greyed out before moving on past the dialog. I'm wondering if I should do a fresh Vitis install...
  8. Hi, I've been following the 'Getting Started' (link https://reference.digilentinc.com/vivado/getting-started-with-ipi/start?_ga=2.217466399.800632162.1585244023-1553730059.1584650870 ) and even though it still discusses the Xilinx SDK, I am trying to create a new Vitis Application Project instead. The Vivado creation of the XSA file seems to go fine. However, when on the Vitis 'Templates' dialog, I go to the 'Create a new platform from hardware (XSA)' tab, I browse to my XSA file (created during the getting started link, select the browsed to item, then click 'Next'. Vitis does *something* (not sure what, then I click 'Next', and then the 'Next' button gets greyed out and I can't do anything else. Any help with why Vitis doesn't allow me to move on with creating the Application Project much appreciated. Note 1: I cross posted this in the Xilinx forum. Note 2: I found this related forum entry and it's on step 9 that Vitis won't let me advance. Peter
  9. Thanks JColvin. I'm actually looking at both now. Thanks for the pointer (*).
  10. Hi all. I've done a lot of microcontroller dev in the past. Some FPGA dev but this was several years ago. Have been doing mostly Visual Studio dev for the last several years. Anyway, back in FPGA dev now and working with the ZyboZ7 and ArtyS7 boards. Have the latest Vivado 2019.2 and whatever the current Vitis is (not the Xilinx SDK ). Steep learning curve. Seems I've been reading non-stop for about a week. Although I feel pretty good about my VHDL and C skills, I haven't been able to get a simple project working that simply sends characters over a UART. I'm sure I'll ask a lot of dumb questions - and hopefully soon can contribute answers. Glad to be here! Peter