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  1. So I've got it working. Not exactly thrilled with it yet (it seems a bit fragile since I'm not sure what everything is actually pointing to and I need to do some better documenting/moving around). I mentioned my old HDD was corrupted - it wouldn't boot (and it was smaller than I needed). Turns out most of the file system was still intact. And luckily for me, my laptop (which is my dev computer) had the ability to have two SSDs. So I connected the old drive (now D) and was able to actually see most of the old file system. Turns out I was using 2019.2 Vivado and Vitis. I was able to r
  2. (I just saw @JColvin post so I'll get the 2019.1 version next. :-) In the meantime, since I bothered to do the following, I thought I'd post it)... OK. so I tried the same things on 2019.2 (Vivado and Vitis). I restored a 'fresh' copy of the projects that were successful on 2019.1. Perhaps I've got a setting not configured correctly in Vivado. The Synthesis, Implementation, and Bitstream portions of the flow all complete successfully (no errors, some warnings though). I then go to File->Export->Export Hardware (note I haven't exported the bitstream)to export the Hardware,
  3. That's a great idea I hadn't thought of. It doesn't look like 2019.1 is available on the Xilinx website. But 2019.2 is. Let me give that a try and I'll post back.
  4. Thanks for taking the time to post that, @zygot. Odd that for this project, the IP in question were/are both Xilinx items (the ZYnq7 processing system and the Processor System Reset, both of which indicate 'no changes' between versions). I started over with a fresh copy of the original project that worked with Vivado 2019.1. I've been able to Update IP, Run Synthesis,, Run Implementation, and Generate Bitstream without seeing any apparent errors. I hate when things seemingly resolve themselves like this since I have no idea what caused it or why it seems to work now. The Vitis ap
  5. I forgot to attach the picture of the dialog that pops up when I click 'Retarget IP'. I've looked for the 'upgrade flow' (and googled it) and have found nothing.
  6. There is. It says 'Selected IPs can't be upgraded'. (which I hadn't seen before). The icon next to those IPs has a little red 'lock' symbol next to it. Not sure what it means (the Vivado docs haven't been helpful in that regard, yet, at least).
  7. My target is the Zybo-Z7-10. I have been away from embedded dev for some months. I also had a HDD crash so I'm working with a new drive. I was using Vivado2019.1 (and the associated Vitis) for a project. With that version of Vivado, I could go through the whole project flow and create the appropriate .xsa file for the project, then could do Vitis development for the generated hardware. When I re-imaged the computer with new HDD, I downloaded Vivado2020.1.1 (and associated Vitis). I also downloaded/copied/pasted the Digilent board files to the appropriate location in the Vivado direct
  8. I've been making reasonable (good, even) progress with the Vitis IDE and the ZyboZ7. A question though about clocks on this board and their interface to the Zybo. I've been using the xscutimer module in interrupt mode. However, I'm struggling to figure out appropriate values for the TIME_LOAD_VALUE. If I set it to a pretty high number (hex FFFF FFFF) (dec 4,294,967,295), I see events happen at about 0.8s. If I set it to 9FFF FFFF (dec 2,684,354,559), I see an event about every 0.5s (they scaled pretty linearly). Since I believe the timer is just counting this many clock cycles, i
  9. Hi JColvin. That's somewhat useful. 🙂 I did start a thread over at the Xilinx forum on a design choice. After more studying of the example (and Xilinx UG480 which seems to have been it's basis), it *seems* the configuration is all done with those hex values you mentioned (though I think they are 32 bits wide, not 16?). I do expect to ask a similar instantiation question over there, after a discussion of a design choice and whether custom IP instantiations of the wizard of inclusion of the wizard as a top level block is a better design choice.
  10. Some very useful info is in XIlinx UG480, particularly page 22. https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
  11. Finally got back to trying this, JColvin. Still have questions. The 'top' design source in the example is a verilog one. What I missed was the entity xadc_wiz_o in the other design source VHDL file. Since I'm still grappling with hierarchical designs (getting there though!), I'm not sure where it came from (it has a Xilinx header but not sure if the Digilent author of the 'top' design source just included that header. I copied the xadc_wiz_o entity file below to make it easier for me to ask my questions (I might have violated a message board rule by copying the whole file - sorry
  12. Hoping for a bit of explanation on this example. I've been focused on VHDL, not verilog (which looks like the language of this sample). Question... how does the module 'top' know of the existence of myxadc (which is an instantiation of xadc_wiz_0 (or vice versa since I'm not sure the order of verilog statements))? IOW, I don't see a reference, include, using, etc... module top( input clk, input [7:0] ja, output [3:0] led ); reg [6:0] daddr = 0; // address of channel to be read reg [1:0] ledidx = 0; // index of the led to capture data for wire eoc;
  13. So I've made a pretty simple IP block in a Zybo design that also contains a Zynq processing system IP. I'm interested in the button presses and slide switches to serve as inputs to both the PL and PS and to control the LEDS - 2 each - from the PL and PS. Struggling to figure out how to get the connections for this. Can anyone point me to a tutorial (or sample project) for the Zybo that does something similar, please? (I should have mentioned I'm using Vivado 2019.2 and whatever the current Vitis is).
  14. Hi Ana-Maria, I forgot to respond to your post (though do thank you for your response). Not sure why the light-bulb didn't go off before. Peter
  15. Thanks, JColvin. FWIW, I have the -10 version of the ZYboZ7. The example you pointed to was somewhat helpful. I need to study it a bit more but think it will be very useful. In the meantime - and because I need to do it anyway as part of this simple design - I've moved back to connecting a simple custom IP block to a Zynq and continue to have some issues. I'll ask in another thread if someone can point me to an example.