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About Quemar

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  1. Hi @JColvin, Thanks, for your feedback. On our side we confirm than due to the output level shifter buffer on the TCLK of the JTAG-SMT3, this JTAG probe is not compatible with Lattice. If we remove this buffer, the probe became compatible with Lattice. On our first version of the board we had the luck or the unluck that it worked ! To go ahead, we are interested to implement the FTDI chip as a Digilent JTAG probe compatible with Xilinx. As already asked in this tread, is it possible to buy a Digilent licence in order to design our own JTAG probe? Thanks for
  2. Hi @JColvin We made the following measurements on the JTAG-SMT3 module which is on our board. All the scope print screen are done with the following configuration: In yellow: TCLK on the output of the JTAG-SMT3 module, pin 10. (After the LS buffer) In blue: TCLK on the FTI FT2232H chip pin 16. (before the LS buffer) In red: TMS on the output of the JTAG-SMT3 module, pin 13. In green: DATA out on the output of the JTAG-SMT3 module, pin 12. 1. Measurement done with Xilinx Vivado debugger tool: All the signals are correctly driven and the JTAG c
  3. Hi all, We found the cause of our problem without understanding exactly the problem. The problem comes from the level shifter on the TCLK which is not driven with diamond but is with Vivado. The TCLK is correctly generated on FT2232H side, but does not pass through the level shifter. Maybe because OE for TCLK is not correctly driven? But Why? And why with other JTAG-SMT3 the TCLK is working correctly? Are you sure there is no different versions of the JTAG-SMT3? Could you provide us the schematic and the layout, thus we could investigate? (Revert engineering on a
  4. Hi @JColvin, The main conclusion of all this problems is that we can't integrate your JTAG-SMT3 probe in our design. We don't know why but it's like that... We need to intergrade our self JTAG probe compatible with Xilinx and Lattice tools on our board. For that, we will implement our own design based on a FTDI FT2232H and for that I think we need to buy a Xilinx-Digilent licence ? Could you give me the procedure or the contact to discuss with to buy such licence ? Thanks, Marc
  5. Hi @JColvin, Thanks for your feedback. I've already done lots of your advices last week: - We tested with many version of Vivado HWdebugger and Diamond programmer and it was always the same result. Always ok with Xilinx and not with Diamond - We are always able to access all the chain with Vivavo whatever if the Lattice is programmed or not or if we previously used diamond or not. - We tried with different clock speed and this has no impact (always the same result with Vivado and Diamond) - We have probed all the JTAG signals and we think there are "electrically
  6. Hello all, I am facing a strange issue. I am using a JTAG-SMT3 probe on my product to program the following components: On the first prototypes all was working fine: - I am able to program Xilinx FPGAs with Vivado - I am able to program Lattice MachXO2 with diamond programmer On the second batch, I am always able to program with Vivado but unable to do a simple boundary Scan with diamond. I've replaced the JTAG-SMT3 by a Trenz TE0790 on one board and it is working fine with diamond programmer. The JTAG-SMT3 probes don't come from the same command/ba
  7. @grymoire666: Yes I know. But if you want that your FT2232H chip is recognized as a Xilinx JTAG cable you need to flash a serial number in the EEPROM. And this serial can't be programmed with FT_PROG. I'm still waiting on DIGILENT answer to understand how to proceed to buy such serial... They are not very reactive ...
  8. Hi, Thanks. You do not sell pre-configured EEPROMs, but do you sell a solution to configure a FTDI chip (for exemple FT2232) as a USB JTAG compatible with Xilinx tools. I need to implement (on my board) a JTAG probe + UART interface (for debug) compatible with Xilinx tools. Do you provide such solution ? Marc
  9. Hi, do you also sell the bare EEPROM (type like 93AA56BT) preprogrammed for use with JTAG+UART on FT2232? Best regards, Marc