Michael Astahov

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About Michael Astahov

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  1. Im using Lattice FFT Compiler I didnt see in the datasheet a way to insert 2 samples per clock cycles. nevermind I have results using 2 FIFOs and mux to switch between the FIFOs data to the FFT. I thought maybe there is a better way. thanks for the help FPGA-IPUG-02045-2-1-FFT-Compiler-IP-Core.pdf
  2. I appreciate the help. Im using Lattice ECP3, Ill try to explain myself again, my english is not perfect. I do not working on both clock cycles, but my ADC is providing me data on both clock cycles, I attached figure below from my ADC datasheet (ADS5463), Im already using I/O High Speed Interface (GDDRX1_RX.SCLK.Aligned) that latching the 12bit data from the ADC and outputs every clock cycle 24bit bus, I attached figure for this interface architecture too. the clock Im using is external and not important for now.. lets assume my sampling frequency is 100MHz so the FPGA gets 50MHz clock. I already did synthesis tests on my data until now (using Reveal Analyzer that Lattice have in their Diamond program).. everything working fine until now, I do getting all the data from the ADC to the FIFO ann from the FIFO output. The point of my question, is how I should use this 24bit bus to continue use the ADC data in the FPGA (for example provide the data to the FFT).. because the 24bit bus as is not helping me, I need 12 bit data because only the 12bit data is meaningful point on the sine wave. so for example if I creating 24bit width FIFO, what can I do next with this 24bit data? I need only the 12bit data, How can I use all the data without losing half of the data.
  3. so you saying there is a way to fill 2 cells of the FIFO in 1 clock cycle? for example, ADC data coming in buses of 24bit, in rising edge clock Im latching the data to the FIFO so 1st cell of the fifo is adc_data[11:0] and 2nd cell of the fifo is adc_data[23:12] ? I didnt find such technique in the lattice documantations but if you say there is a way for sure ill further explore.
  4. The sampling clock is 400MHz (the clock going to the ADC) but the clock coming to the FPGA is the DRY signal from the ADC (200MHz). The ADC working in DDR mode, so I saving the negative edge and positive edge data in diffrent FIFOs, the FIFOs is sync using one clock (200MHz). Im writing to the FIFOs until they fill up (full signal assert) and the FFT reads the data from them (1st clock cycle -> positive edge fifo, 2nd clock cycle-> negative edge fifo.. and so on). I think I have to use 2 FIFOs because the DDR interface latching the 12bit ADC data to 24bit bus, so I need to seperate the data before Im using it.
  5. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for the negative edge data. My next step which Im currently working on is to insert this data into the FFT IP module which Lattice provides. (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiBl_HfzovoAhVKY5oKHfNPBt0QFjABegQIAhAB&url=http%3A%2F%2Fwww.latticesemi.com%2Fview_document%3Fdocument_id%3D28236&usg=AOvVaw3HSzLdNneCLsy5wEoUnUOx) I attached timing digrams (timings.pdf). The FFT IP Im creating is 12bit width input/output so I need to time the input flags in a way that it take first data from the positive edge FIFO and the next data from the negative edge FIFO and processing so on in a stream. Of course Im paying attention to all the flags as the IP telling. I want to ask some guidelines questions about how to do it correctly. 1. Do I need a state machine which indicates when the FIFO is full and only then to read the data into the FFT input? Or I can start writing to the FFT without state machine and just counter register which indicate when is read enable asserted and start reading to the FFT? 2. Do I need to fill the FIFO and then read the data until its empty, or I can write to the FIFO and read from the FIFO to the FFT continuously? 3. Any guideline how to make this task correctly? I never did this before.. From my prepective I would just wait for ready flag from the FFT IP and read_enable from the FIFO and start to provide data to the FFT IP but I told the there is more timing managment to be made. thanks. timings.pdf