yildizabdullah

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  1. @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  2. @D@n I work on ISE and possibly I am doing something wrong in my SPI Flash controller. Thanks for your suggestions.
  3. @D@n @jpeyron Do I have to include a pin constraint for spi_clk in .ucf file? I suppose I have to, but get an error during Implement Design step in Xilinx ISE as ERROR:MapLib:30 - LOC constraint E9 on spi_clk is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
  4. I get an error during Implement Design step in Xilinx ISE as ERROR:MapLib:30 - LOC constraint E9 on spi_clk is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. When I place a location constraint for spi_clk pin which is input to my top module.
  5. I need to read from Quad-SPI Flash device on Nexys A7. Reference manual has the following statements: All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. How can I utilize the STARTUPE2 primitive in order to drive SCK pin properly during a read operation?
  6. I need to use Nexys2 onboard RAM for a project. Since I am not familiar with VHDL, I redesigned the RAM interface in Verilog HDL by using the reference design (NexysOnBoardMemCtrl.vhd) in Nexys2 Onboard Memory controller reference design on Digilent Nexys2 website. Problem Description: I use asynchronous mode both for read and write operations. I can write to memory and can verify it with Adept software. However, there is a problem when reading from RAM: when I initiate a read data operation, I can read the data at the respective address when I initiate another read operation. For example: When RAM is utilized as follows: Addr Data 0x0 0x00000x1 0x00010x2 0x00020x3 0x0003... ... When I try to access the data at address 0x2, I read 0x0001 instead of 0x0002 (if I requested the data at address 0x1 at the previous read operation). I also examined the datasheet of the RAM IC which was not helpful. I attached my Verilog design along with the reference implementation in VHDL. Could anyone help me who previously worked on a similar problem? Nexys2_RAM.v NexysOnBoardMemCtrl.vhd