ejc

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  1. ejc

    PMODSD

    I was trying to use ip integrator and vitis to examine how to write and read to an SD card. I have used the ip integrator with PmodMTDS and PmodKYBD successfully using the example codes supplied. I assume the code is written in c++ and that is what I set the vitis project for. However, with PmodSD the example code in main.cc is not building. After examination, there is one line of code in the example main.cc that is a syntax error, sqiggly lines on the code and when I run the mouse over it, it tells me syntax error. DFATFS::fsmount(disk, szDriveNbr, 1); There are also many syntax error in the #include "DXSPISDVOL.h". practically half of it has the squiggly lines. Below is what I get when trying to build the project. Description Resource Path Location Type make: *** [makefile:50: sdtest.elf] Error 1 sdtest C/C++ Problem region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 63000 bytes sdtest C/C++ Problem sdtest.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' sdtest C/C++ Problem So if the syntax errors are causing this, what is the fix? I am using ARTY A7 with 35T csg324 board.
  2. ejc

    vitis

    I have just successfully completed the getting started with ip integrator and even changed some things to make the leds do something different. So I have a general idea of how you use the ip integrator from start to programming the board. However, I have a question. Normally in C you use a printf statement to print on the console, but in vitis you use xil_printf. If I didn't have a C program already made for me, as in the tutorial, I would have used the printf statement? However, you have to use the Xil_printf statement. Is there a place you can point me to that would have statement syntaxes that are unique for C as used in Vitis so I would know how to talk to the circuit I design in ip integrator? Another example in the tutorial was that you had to initialize the GPIO. How would I have known this unless some instruction told me you have to do this. So this is the information that I am looking for, something that explains to me what special C commands or initializations you have to in order to talk to your ip design. ejc
  3. ejc

    schematic error arty a7

    Thanks. I really appreciate how you point me to the right place for information that would of otherwise taken me much time to find. I never did find the 2019 .2 getting started. I only found lots of older stuff form 2015 to 2018. Thanks again EJC
  4. ejc

    schematic error arty a7

    I finally figured it out.
  5. ejc

    schematic error arty a7

    Hi I decided to try using ip integrator instead of writing code in Verilog. I am new to this. I am at a loss for how to get the boards window or tab to work. It is grayed out in the windows menu of the vivado 2019.2 program. I did try following directions on the website about downloading board files and installing the tcl files with a path to where they were downloaded, but it isn't working. I am using the artix-7 35t csg324 fpga board. I could use some simple instructions on how to resolve this so I can move forward with learning it. I tried YouTube, but it seems like in their it videos it just works. But they use an older version of vivado than 2019.2.
  6. ejc

    schematic error arty a7

    I see that these pins are connected to the config. I thought that perhaps I could use the shield pins as an additional pmod output or input. However, if I do this will it upset anything in the arty a7 since these 3 pins are connected to the config?
  7. ejc

    schematic error arty a7

    I was trying to identify the net pins to the FPGA(artix-7 35T csg324) connected to the shield io pins on an Arty A7 board. The schematic left out io0, io34, and io7 or at least I have been unable to find them. Can someone help me identify what the fpga pins are so I can setup my constraints? ejc