• Content Count

  • Joined

  • Last visited

  1. dfdias


    Hum ok I will try. That actually makes sense, although when opened a debug session I saw that the register containg cpha and cpol was as it should be. Thanks in advance. I will reply as soon as I test it.
  2. dfdias


    Hi was trying to interface the accelerometer available on the nexys 4 board. But i was not getting any data. Then I mapped the output pins to the JA PMOD header so I could probe them Using an logic analyzer I saw that the sclk and Chip_select were working but the MOSI signal is full of zeroes. I connected an 50MHz clk coming from the clock wizard, and then connected it to the ext_spi_clk and used an scale of 16 so the clk is about 3.16MHz Below is the Block_Design helloworld.c Below is the data I acquired using saleae logic analyzer: