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  1. I have a mostly working HLS and Zynq project, where the custom HLS block takes in 8 16-bit values (from external ADCs) and then transmit these 8 values to a DDR memory location. Right now, I have dummy constants as the 8 inputs for testing: Now, when I trigger the VIO (connected to the "go_flag"), I DO get an AXI memory transfer, but it transfers the decimal value "11" across all 8 memory locations: So the first constant value is working, but the next seven are copies of the first. Is this some kind of HLS "optimization" or caching problem? I'm not sure why this is. Here is
  2. Okay, I *think* I have it working now. Let me answer myself here, for documentation purposes (for anyone else who may have this problem): 1. In the SDK, Go to "Run"-->"Run Configurations" 2. Under the "Target Setup" tab, find the "Initialization File" white bar. Initially, my bar was blank (meaning no initialization file was used). I have now ADDED my ps7_init.tcl file to this ( Your_project_directory\your_project_name.ip_user_files\mem_init_files\ps7_init.tcl ) 3. Once the .tcl file is added, check the "Run ps7_init" and "Run ps7_post_config" checkboxes. Screenshot
  3. Hello All, I seem to be going backwards in my testing with Vivado and the SDK. I can no longer get into debugger mode with the SDK. I have reverted to a known "good" design that DID program and debug yesterday, but today, this too gives me the same error when I try to debug it. My steps are: 1. "Build All" in the SDK 2. Program the FPGA (no problems here) 3. Click on Run->Debug As->Launch on Hardware (System Debugger) I get a "Memory write error at 0x100000. Cannot access DDR: the controller is held in reset" ---- After doing some research (Xil
  4. Greetings All! I'm trying to write my own verilog custom IP in Vivado for interfacing with an AD7606 ADC (8 channels, 16 bits, simultaneous sampling). The basic idea of my timing diagram is as follows: -Raise the CONVSTART pin from an EXTERNAL source (conversion will start on a positive edge) [Verilog module starts in an IDLE state] 1.Wait for the negative edge of the "BUSY" input pin from the AD7606 2. Drop !CS (chip select) LOW 3. Drop !RD (read) LOW, wait at least 100 nanosec 4. Raise !RD high, read channel 1 result, wait a least 100 nanosec
  5. Thank you for your help Eduard! I am still stuck on this issue, after using Xilinx's example code, as well as the XScuGic_SetPriorityTriggerType(IntcInstancePtr, IntrId, 0xA0, 0x3); function that is supposed to set interrupts on rising edge only. - Everything on my board is working (AXI Gpio 0 [my buttons] are inputs, AXI Gpio 1 are outputs, AXI Gpio 2 are outputs) - The interrupts are firing based on axi gpio 0 (which is connected to my pushbuttons), - My PWM block is outputting a PWM waveform that triggers the interrupt (I soldered a jumper wire from the PWM ou
  6. Aha! I think I found my mistake - I need to click on "Make Exernal" on the "gpio_io_t[:]" port (this makes a black wire), NOT the GPIO port (this makes a blue wire). Thank you again for your help Eduard!
  7. Thank you for your help Eduard! I have deleted the original "buttons" port, and I right-clicked on the AXI "GPIO"-->Make External. The port I named as GPIO_0, and the AXI port is only 1 bit wide (see screenshot). In my constrains file, I want to set this new pin to A1 of the schematic, so I have: set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { GPIO_0[0] }]; #IO_L20P_T3_13 Sch=CK_A1 When I try to generate the bitstream, I get the following error: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is great
  8. Greetings All! I'm working through the basic tutorials on the AXI GPIO blocks, and interrupts, with the Arty Z7. In the current design using axi_gpio_0, pressing any of the four pushbuttons does cause an interrupt in my code (great!). Now, I want to move the gpio_0 input to another pin (say, A1 on the Arty Z7 board - I'm not using the XADC). I see that the GPIO part of the gpio_0 block is a bus (a 4-wire bus in this case, that goes to 4 buttons). Now, I only want to use 1 wire of gpio_0 to connect it to an output port (which will be A1 in the constraints file). Do I use a slice I
  9. Greetings All! Using an Arty Z7, I'm trying to migrate a real time motor control application from a microcontroller to the Arty Z7. My goal is to eventually implement the inner current control loop (running at 20kHz) in the PL fabric for high speed using Vivado HLS, while one of the two A9 cores runs the slower tasks (like velocity control), and the other A9 core runs the user interface. With the real time determinism in mind, do I want to make my PL interface bus with an AXI4 "full" implementation, AXI4-Lite, or AXI4-Stream? From what I can see in the Xilinx App notes, AXI4-Stream
  10. Greetings All! I have an Arty Z7, and I'm following michael ee's online tutorial for GPIO interrupts here: https://www.youtube.com/watch?v=JPVTVNtJ7R4 Everything works - mostly! I have a dummy counter in the interrupt handler. When I press and release a button, the dummy counter increases by 2. This tells me that the interrupt is firing on both positive and negative edges. Is there an XGpio function, that tells the handler to trigger only on a certain edge (positive or negative, not both)?
  11. Hello All, Me again, with a basic "getting started" question. In the Arty Z7 and Zybo examples, there are interrupt examples that use the external buttons on the AXI GPIO (pressing any of these buttons on either board can cause an interrupt). I want to use all of the GPIO pins on the GPIO0 port of the Arty Z7 board (which are labeled DP0-DP13), but let's say I only want to attach an interrupt to one of them. Example: DP0 - DP6 are inputs, DP7 - DP13 are outputs. Attach a positive edge triggered interrupt to DP6 ONLY. Is there an example that shows how to do this?
  12. Greetings! I have been through several of the basic "getting started" tutorials with the Arty Z7 board (so far, so good). Now, I want to use the shield pins on the Arty Z7 (no buttons or LEDs), so I have added two GPIO IPs to my block diagram (see attachment for block diagram). Eventually, I want to add interrupts to these GPIO pins. When I do this, I get this list of warnings: WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/vivado-boards/new/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part
  13. Sorry everyone - I win the sucker award for bad post. I had the wrong board chosen as the target (I chose the Arty A7 board, which does NOT have an onboard Zynq processor).
  14. Greetings All! Basic question here - I'm following this tutorial: https://reference.digilentinc.com/vivado/getting-started-with-ipi/2018.2 (I'm actually using Vivado 2020.2) In my block diagram, when I "Add IP" and search for Zynq, I do not see anything for the Zynq processing system. Am I missing something? (Screenshot of "Add IP" menu attached)
  15. Greetings all! I have ordered an Arty Z7 (7020), and I'm looking around for some basic C or C++ examples to be used with it. As a learning example, let's say I ONLY want to use the Arm dual core processor (no programmable logic, and no Linux operating system). Is there a bare metal example that shows a basic interrupt, or a "ping pong" variable exchange between the dual cores?