Vik

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  1. Thanks J. It was great help and I am able to get past the initial hump.
  2. I understand quite a few things have changed with the SDK to Vitis migration on the software side. But, I am having trouble with the hardware also I followed this tutorial and I get two error while trying to generate bitstream https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Any help is greatly appreciated. Thanks in advance The error message is as follows - [BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'system.bd' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_stat