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  1. I have not made any changes on the SDK code itself, I am using the "echo server" application that can be created and generated by anybody that are using the xilinx sdk application.
  2. Hi, After several hours of trail and error, trying to debug and understand what the problem is, I finally managed to get it to work! The solution was as you've mentioned with the MII mode. I had to set the eth_rx_dv pin manually to high to set the PHY into RMII mode, this was solved finally by creating a gpio block with one output and setting the default value to 0xFFFFFFFF. Afterwards the rmii mode was activated! Thank you for all the help @toshas!
  3. I have tried to set the pin as pull-up, but I'm unsure whether this is correct or not?
  4. Hi, Thank you for all the help, I really appreciate it Ok I'll try 50MHz clock reference instead. However, if I remember correctly I had some problems getting the ethernet port to work as it was giving me on the pc that the ethernet port was off, will give it a try again anyways. Might be something with the pull-up as you've mentioned, as it needs to be switched to rmii mode Regarding the ethernet port, I am using the arty a7 35-t dev board which has a ethernet connector by default onboard, same as can be found in this link: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual
  5. Yes, that's correct. I had excluded both rx[1] and tx[1] from the constraints and the ports, however, when I connected the ports to the ip core block it marked them as [1:0] so added just tx[1:0] but not rx. I have now tried to add it in the constraints file, both rx and tx -> [0] & [1], and also changed the ports to range from 0->1, but, still I'm not able to connect to the device. I Have also tried to change the configure_IEEE_phy_speed_emaclite function, to the register as per suggestion(0x17), but still can't connect. The configurations inside the constraints file seem to be correct, I have used the master file that I've found on digilent's github and also i'm using the onboard ethernet that is soldered on the arty a7 35-t. I the eth_ref_clk is set to 25MHz, is it right or should I be doubling the frq? create_clock -add -name phy_clk -period 20.00 -waveform {0 10} [get_ports ref_clk] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ref_clk_IBUF] ## SMSC Ethernet PHY set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { phy2rmii_crs_dv }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports { eth_ref_clk }]; set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { phy2rmii_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { phy2rmii_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1] set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { phy2rmii_rx_er }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { rmii2phy_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { rmii2phy_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { rmii2phy_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
  6. Thanks @toshas! I'll check the files and get back with an update.
  7. Hi @toshas, Thank you for the help! I have tried to modify xemacliteif.c source file with suggested changes you proposed, but still have the same problem. I am using the ethernetlite core connected to a mii->rmii core as can be seen in the image in the first post. Also, I am running xilinx vivado 2019.1, sdk is also the same version The arty a7 35-t board I am using, is utilizing an TI Ethernet PHY (DP83848), not DP84838 as in your case unfortunately- My configure_IEEE_phy_speed_emaclite function in xemacliteif.c file looks like this without any changes: (I am using a fixed speed (100), as suggested by the digilent tutorial I originally followed) unsigned configure_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep, unsigned speed) { u16 control; u32 phy_addr = detect_phy_emaclite(xemaclitep); XEmacLite_PhyRead(xemaclitep, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); control &= ~IEEE_CTRL_LINKSPEED_100M; control &= ~IEEE_CTRL_LINKSPEED_10M; if (speed == 100) { control |= IEEE_CTRL_LINKSPEED_100M; /* Dont advertise PHY speed of 1000 Mbps */ XEmacLite_PhyWrite(xemaclitep, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0); /* Dont advertise PHY speed of 10 Mbps */ XEmacLite_PhyWrite(xemaclitep, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, ADVERTISE_100); } else if (speed == 10) { control |= IEEE_CTRL_LINKSPEED_10M; /* Dont advertise PHY speed of 1000 Mbps */ XEmacLite_PhyWrite(xemaclitep, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0); /* Dont advertise PHY speed of 100 Mbps */ XEmacLite_PhyWrite(xemaclitep, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, ADVERTISE_10); } XEmacLite_PhyWrite(xemaclitep, phy_addr, IEEE_CONTROL_REG_OFFSET, control | IEEE_CTRL_RESET_MASK); { volatile int wait; for (wait=0; wait < 100000; wait++); for (wait=0; wait < 100000; wait++); } return 0; }
  8. Hi @JColvin Thanks for the reply! I am currently using vivado 2019.1 and indeed the block is discontinued. Does this effect anything when I am trying to use reduced mii? The application was working without any problems when using only ethernetlite, but when I integrated the mii2rmii I am not able to get any connection with the application server or able to send anything to the device. I am successfully able to generate the bit file and am not getting any errors when generating it. I have the following constraints that I extracted from the master file for arty 35-t: set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1] These different ports are then created in the diagram as seen above in the picture Besides from this I have also tried to add the following lines inside the constraints file according to the following guide https://www.xilinx.com/support/documentation/ip_documentation/mii_to_rmii/v2_0/pg146-mii-to-rmii.pdf create_clock -name Ref_Clk -period 20 -waveform {0 6} [get_ports Ref_Clk] create_clock -name Rmii2Mac_tx_clk -period 20 -waveform {0 6} [get_ports Rmii2Mac_tx_clk] create_clock -name Rmii2Mac_rx_clk -period 20 -waveform {0 6} [get_ports Rmii2Mac_rx_clk] set_property IOB TRUE [get_ports phy2rmii_rxd] set_property IOB TRUE [get_ports phy2rmii_crs_dv] set_property IOB TRUE [get_ports phy2rmii_rx_er] set_property IOB TRUE [get_ports rmii2phy_txd] set_property IOB TRUE [get_ports rmii2phy_tx_en]
  9. I have now managed to build and generate the bit file, however when I run my echo server application I can't seem to get any connection the board. Before when I only had the the mii ip block I managed easily to connect to the server and send messages, however, now I am not getting any connection with the echo server. Is there something I'll have to do in order to establish any connection and send messages?
  10. Hi, I am trying to add the rmii ip component into my design and am having problems getting it to work. When I try to map the IO:s I get a lot of problems such as : I have tried the following, but neither worked Tried connecting the two IPs together like this by just connecting them: AND also tried to manually set the values inside .xdc file and create ports to each ports:
  11. Hello @Ana-Maria Balas, Thank you, that fixed the problem with the with the code halting and not continuing. Regarding the second problem with GPIO interrupt not triggering with FreeRTOS. It seems that I needed to enable also interrupts in Freertos with the following commands vPortEnableInterrupt( XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR ); After the software is triggering interrupts everytime the pin is driven high. Thank you for the help!
  12. hdx

    Arty a7 35t spi pmod

    HI @Ana-Maria Balas It was indeed what was causing the data to not be sent accordingly, noticed this after debugging with a logic analyzer. I have managed to fix this and can now see the correct data when debugging with a Logic analyzer. Thanks for the help!
  13. Hi I am having problem with gpio interrupts on arty a7 when using rtos. I have mapped a pin to a gpio ip to trigger an interrupt on pin IO7 when it is drawn high. When I run the code, the initialization succeeds without any problem and I can see the first character being printed out inside the interrupt and then freeze. If I then rerun the code, without programming the FPGA with bootloop, the interrupt doesn't trigger and get stuck at microblaze_enable_interrupts(); If I run my code in a non rtos application it runs fine and triggers the interrupt without any problems. Would appreciate any help I could get to get the rtos application to run with gpio interrupt
  14. hdx

    Arty a7 35t spi pmod

    Hi everyone, I am having trouble getting SPI to work on the arty a7 35t dev board with a mc33972 module. I have created a design consisting of an AXI QUAD SPI module and created ports that are connected to the pmod ja port. When I connect the pins of the ja port to the mc33972 module and send a message I don't get any response back. The XSpi_Transfer function pass without any problem but there is nothing coming out on the ja port. set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { SPI_CS }]; set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { SPI_MOSI }]; set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { SPI_MISO }]; set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { SPI_SCLK }]; XStatus SpiInit(XSpi *SpiPtr) { XStatus Status; XSpi_Config *ConfigPtr; Xil_AssertNonvoid(SpiPtr != NULL); /*ConfigPtr = &SPIConfig; if (ConfigPtr == NULL) { return XST_DEVICE_NOT_FOUND; }*/ ConfigPtr = XSpi_LookupConfig(XPAR_SPI_1_DEVICE_ID); if (ConfigPtr == NULL) { return XST_DEVICE_NOT_FOUND; } Status = XSpi_CfgInitialize(SpiPtr, ConfigPtr, ConfigPtr->BaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } Status = XSpi_SetOptions(SpiPtr, XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION ); if (Status != XST_SUCCESS) { return XST_FAILURE; } Status = XSpi_SetSlaveSelect(SpiPtr, 1); if (Status != XST_SUCCESS) { return XST_FAILURE; } // Start the SPI driver, enabling the device Status = XSpi_Start(SpiPtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } return XST_SUCCESS; } XStatus SPIWrite(PmodSPI *InstancePtr, u32 WriteCmd, u8 **BufPtr) { XStatus Status; // Prepare the buffer with write command data u8 Buffer[3] = {0}; (*BufPtr)[0] = 0x0; Buffer[0] = (WriteCmd >> 16) & 0xff; Buffer[1] = (WriteCmd >> 8) & 0xff; Buffer[2] = (WriteCmd >> 0) & 0xff; Status = XSpi_Transfer(&InstancePtr->Spi, Buffer, NULL, 3); return Status; } int mc33972_init(PmodSPI *InstancePtr) { u8 Status; u8 *ReadBufferPtr; Status = SPIWrite(InstancePtr, CMD_RST, &ReadBufferPtr ); xil_printf("CMD_RST = %d\r\n", Status); if (Status != XST_SUCCESS) { xil_printf("CMD_RST failed %d buf = 0x%02x\r\n",Status); return XST_FAILURE; } sleep(1); Status = SPIWrite(InstancePtr, CMD_CALIB, &ReadBufferPtr ); xil_printf("CMD_CALIB= %d\r\n", Status); sleep(1); Status = SPIWrite(InstancePtr, CMD_STATUS, &ReadBufferPtr ); xil_printf("CMD_STATUS= %d\r\n", Status); sleep(1); xil_printf("mc33972 Done! status = %d\r\n", Status); return Status; } Am I missing something important that should also be specified? Have also tried some of the spi pmod examples and used the correct ports out but still not seeing any data. EDIT: Jan 23 15:57 I noticed that the code I used in spi_write returned XST_SUCCESS instead of status (Have changed it in the code above now). When I ran the code it returned error code 21 = busy. So it seems like xspi_transfer is performed once successfully and then nothing afterwards, just error 21 (busy) rest of the time. I also noticed that I didn't have the XSpi_IntrGlobalDisable(); in the init. If I added that to the init code, then the xspi_transfer() function wont return and will get stuck. Any idea why the function xspi_transfer won't return??? EDIT: Jan 24 08:50 Never mind the edit above, was my mistake. Had set the wrong base address and also id, therefore resulting in failing and not working. However, now xspi_transfer is returning with 0 = success but still not seeing anything on the oscilloscope or getting any response... Would appreciate any help I could get in order to get this working