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RCB

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Everything posted by RCB

  1. Hey! Zybo Z7010 is a popular device with very good support here in the forum. I started with Zybo Z7020 over 7010 predominantly because of additional capabilities that I would like to be available for future projects. I have not faced any problems with the board because Digilent has the board support tools for z7020 and the hw/embedded programming experience is similar to the 7010. For hardware design, specific builds target specific boards. It will be very apparent if you are juggling between different boards with Vivado tool. Internal code might be good for building on different devices but if the logic would be compatible for implementation across devices cannot be guaranteed. But Z7010 is a good board to start with. If the whole project is not entirely compatible with your future boards, it at least guides you through logical errors.
  2. Sorry, I missed email notification of your question. I have done something slightly similar to the fft implementation in http://web.mit.edu/6.111/www/f2015/projects/mitchgu_Project_Final_Report.pdf - they have documented it pretty well. I'm sure you can figure other details on the configuration - Xilinx documentation would be of good help too.
  3. Thank you for the thoughtful reply @zygot! _/\_ I'm really impressed with the idea of Tayloe detector for IQ demodulation when I learned it first. Your suggestion in a similar line of thought appears equally impressive. Thanks for the recommendation and for the push to keep looking for simpler answers! Yes, I will first try a small scale experiment with the Zybo I have - to get an idea on the resources required. I'll keep looking up for answers! Thank you so much!
  4. I'm carefully reviewing your comments. Thank you for the wonderful support. This is not a coursework oriented project but a personal one but still as a student. I am looking at resources that would contain details on interfacing external ADCs (zmod) - to analyze its complexity. RedPitaya board appears like an attractive choice too. " I can think of a few potential alternate ways to do this in the analog domain. Of course this depends on your measurement specifications. But it would simplify your signalling interface work and expense." - Can you share your suggestions on any daughter boards for doing it in the analog domain? (plus, reading their o/p to the FPGA dev board for additional processing). Measurement test specifications - I would like to create two sinusoids (5 MHz, phase differed) and compute their phase difference to the order of a degree. At this point, I am being childish and considering only the logic side of the implementation. Accuracy-wise I'd be happy with a degree rounded-off values for now.
  5. Input signals (2) are 5 MHz analog sinusoids - phase shifted. Project requires me to identify this phase difference between them + do some additional computations later. I am open to suggestions. Here are two main paths that I focused my search toward - 1) if there are daughter boards (RF, analog) that can do phase detection and give a digital output to read to the FPGA - would be ideal 2) if I need to interface high-sampling ADCs to sample the 5 MHz analog input and write phase detection logic on the FPGA - involved but I can try - most resources I looked online point FPGA for phase detection in digital domain I currently have a Zybo 7020 board with sampling rate of 1 MSPS and on-board clock of 100 MHz - insufficient resources (workaround available with this board?). I am familiar with Xilinx environment and prefer to stick with it but open to options that meet my project goals. I would really appreciate your kind suggestions.
  6. I am working towards a phase difference detection project to be developed on FPGA. I have Zybo Z7020 board. ADC sampling rate of 1 MSPS. My input signals are of frequency 5 MHz to 10 MHz. Zybo, unfortunately, is not equipped to sample such high frequency signals. I am unable to find external pmods or evaluation boards that can do phase detection (be it analog RF side or digital). Does anyone here have any suggestions for me to look up for? I'm also wondering if there could be any daughter boards that handle high frequency analog signals (ADC + mixers + filters (or) just ADCs) and hand over the digital data at a (programmable) lower frequency to the Zybo board. If none of the options work, I might painfully move on to a different FPGA evaluation board (Terasic + Intel) and development software (Quartus). Any suggestions/thoughts on different development board specifications with such support would also be really helpful! Thanks! If anyone here worked with NI PCI 5640R - how difficult is it to understand its programming for my application?
  7. FFT IP: 4096 point, Fixed point, non-real time, unscaled Yes, you may populate the least significant bits with the DDS output. I tried square root operation for handling the FFT core output.
  8. Hey @petriggg I am still debugging some blocks and hence decided not to document with bugs.
  9. Hi @D@n I think I got the design right after some experimentation. My mistake was about handling the real and imaginary components. Thank you for your suggestions. I'll document the steps and post it here hopefully soon. Appreciate your help. I would move on with replacing DDS synthesizer with XADC to test external signals with a function generator. - Ram
  10. Hi @D@n I still am facing issues with the design and request your help. I think the problem is with how the xfft core handles the input (32 bit) data. Some information on my input data: 1) Output of DDS compiler: 16 bit sine wave (DDS input 100 MHz clock, output: sine 100 KHz) 2) 16 bit o/p from DDS compiler is converted to signed magnitude form (dds_output - 1<<15) and is concatenated with 16'b0 (MSBs). Alternately, earlier I tried with DDS compiler output as is with 16'b0 concatenation. FFT details: 100 MHz clock, 4096, natural order, pipelined streaming and unscaled. FFT magnitude output with signed 32 bit input FFT magnitude with unsigned 32 bit input: magnitude: mag_data[23:0] Dout0[15:0] and Dout1[15:0] are real and imaginary output slices from FFT. Real: 15:0 sliced from 64 bit FFT output Imaginary: 47:32 sliced from 64 bit FFT output; magnitude being sqrt(real+imaginary)
  11. @D@n I am sorry! The frequency is 50 kHz. My FFT resolution would be (100*10^6)/4096 about 24.5 kHz. X[3] would be the frequency bin with spike.
  12. Hi @D@n @FR can you please help me with my FFT design? Here are the details: I am testing the design with sine wave input from DDS compiler: Frequency 1 MHz. 100 MHz System clock driving DDS compiler, BRAM for storing frame data from DDS 16 bit output and transferring the same data to FFT core. FFT IP core: 100 MHz clock, 4096 point, pipelined streaming, no run time configuration (8'b00000000) & config_tvalid(1'b1), unscaled and testing both bit reversed and natural orders. Block design contains FFT IP core with register slices (64 bit M_AXIS_DATA from FFT is sliced for real and imaginary components as real:15:0 & imag: 47:32) -> multipliers -> add/sub -> CORDIC IP for square root magnitude generation. frame_tlast signal is generated by a 12-bit counter in a bram_to_fft module for frame data transfer. Simulation through a test bench and analysis via vivado waveform viewer. Vivado version 2019.1 I could see that the output of DDS compiler and the input of the FFT module match (image attached). I do not understand the FFT output (the real and imaginary components) and the magnitude data that follows it. Can you point what changes I need to carry out for a correct output? FFT ouput in reverse bit order configuration: I see that the magnitude data (and x_slice_0(real part), x_slice_1(imaginary part)) have bands of waveform of high magnitude followed by lower magnitude values. I was expecting only one spike in the magnitude output. What do you think has gone wrong here? Also, how can I verify this result with regard to expected FFT bin number (on a time based x-axis) and the magnitude value? Output in the natural order (option in FFT IP core) is something like this: I could not make anything of this result. Requesting your help. - Ram
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