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RCB last won the day on April 1

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  1. Thanks @[email protected]! By AXI-stream signaling do you mean the handshaking signals between FFT and post-FFT processing blocks? (Problem with AXI stream register slice may be?) If it was a fixed offset I could account it for the latency in multipliers and CORDIC blocks but a fixed scaling factor is getting me all worried. For the former problem, I could try to add latency to the index signal magnitude_tuser so that both the index and magnitude_tdata have equal latency. I am now unsure about how to start debugging the scaling error. Any guidance would be of immense help! Grateful for your kind support and patience!
  2. Dear @[email protected], I would like to seek your comment on this question: Frequency for xfft aclk: 50 MHz (aclk is 50 MHz) In the below design I am trying to compute magnitude of FFT output (squaring through multiplier and square root using CORDIC). I am probing the signal bus magnitude_out which has the FFT magnitude data and tuser to index bin number corresponding to FFT output. Resolution of FFT is sampling rate/FFT_size: 961KSPS/4096 = 234.7 Hz However, I observe, from direct probing that every frequency component is scaled by 0.8. What I mean is, 100 KHz while expected in the bin number 426, the probed index falls in the bin 341. 10 KHz is expected in the bin index of 42 but the output probe indicates it to be in bin 34 (=0.8*42.6). This linear relationship is observed in all the bin indices. I am not sure of any reason behind this scaling factor. What do you think could be a possible reason for this behavior? Do you have any suggestions that I can check for? Thank you very much!
  3. FFT IP: 4096 point, Fixed point, non-real time, unscaled Yes, you may populate the least significant bits with the DDS output. I tried square root operation for handling the FFT core output.
  4. Hey @petriggg I am still debugging some blocks and hence decided not to document with bugs.
  5. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling rate. If I am not wrong the FFT resolution should be 961.54*10^3/4096 (for a 4096 point FFT). Backtracking from the scope, it appears that there is an offset from the expected sampling rate. Example: While 23.5 KHz is expected to fall in the 100th bin it falls in 111th bin. The sampling rate (computed from the FFT resolution formula - observing output) would be around 870 KSPS. Question 2) Would the sampling rate change if I use a 50 MHz DCLK clock instead of 100 MHz? The IP core indicates that the actual sampling rate would be 961.54 KSPS (same as that with 100 MHz clock) but I observed a shift in FFT output yet again. This time the sampling rate (computed from the FFT resolution formula) falls around 835 KSPS. Please help! P.S. - In my design I used a AXI-4 stream register slice as a pipeline stage to account for latency involved in multiplication and addition operations on the FFT output so that the signals from xfft_0 appear at the same time as the data. Frames are sent at the same rate (100MHz) at which the FFT is operated => BRAM read frequency = FFT CLK = 100 MHz. 3) Question on FFT: My FFT output appears to be almost as expected (except for the constant offset in frequency bins). After every 4095th bin there is a repetition of bin value 4080, (for a certain interval, until next 0) and I with a peak at this value. I do not understand the reason behind this. Please provide some insight on this as well.
  6. Hi @[email protected] I think I got the design right after some experimentation. My mistake was about handling the real and imaginary components. Thank you for your suggestions. I'll document the steps and post it here hopefully soon. Appreciate your help. I would move on with replacing DDS synthesizer with XADC to test external signals with a function generator. - Ram
  7. Hi @[email protected] I still am facing issues with the design and request your help. I think the problem is with how the xfft core handles the input (32 bit) data. Some information on my input data: 1) Output of DDS compiler: 16 bit sine wave (DDS input 100 MHz clock, output: sine 100 KHz) 2) 16 bit o/p from DDS compiler is converted to signed magnitude form (dds_output - 1<<15) and is concatenated with 16'b0 (MSBs). Alternately, earlier I tried with DDS compiler output as is with 16'b0 concatenation. FFT details: 100 MHz clock, 4096, natural order, pipelined streaming and unscaled. FFT magnitude output with signed 32 bit input FFT magnitude with unsigned 32 bit input: magnitude: mag_data[23:0] Dout0[15:0] and Dout1[15:0] are real and imaginary output slices from FFT. Real: 15:0 sliced from 64 bit FFT output Imaginary: 47:32 sliced from 64 bit FFT output; magnitude being sqrt(real+imaginary)
  8. @[email protected] I am sorry! The frequency is 50 kHz. My FFT resolution would be (100*10^6)/4096 about 24.5 kHz. X[3] would be the frequency bin with spike.
  9. Hi @[email protected] @FR can you please help me with my FFT design? Here are the details: I am testing the design with sine wave input from DDS compiler: Frequency 1 MHz. 100 MHz System clock driving DDS compiler, BRAM for storing frame data from DDS 16 bit output and transferring the same data to FFT core. FFT IP core: 100 MHz clock, 4096 point, pipelined streaming, no run time configuration (8'b00000000) & config_tvalid(1'b1), unscaled and testing both bit reversed and natural orders. Block design contains FFT IP core with register slices (64 bit M_AXIS_DATA from FFT is sliced for real and imaginary components as real:15:0 & imag: 47:32) -> multipliers -> add/sub -> CORDIC IP for square root magnitude generation. frame_tlast signal is generated by a 12-bit counter in a bram_to_fft module for frame data transfer. Simulation through a test bench and analysis via vivado waveform viewer. Vivado version 2019.1 I could see that the output of DDS compiler and the input of the FFT module match (image attached). I do not understand the FFT output (the real and imaginary components) and the magnitude data that follows it. Can you point what changes I need to carry out for a correct output? FFT ouput in reverse bit order configuration: I see that the magnitude data (and x_slice_0(real part), x_slice_1(imaginary part)) have bands of waveform of high magnitude followed by lower magnitude values. I was expecting only one spike in the magnitude output. What do you think has gone wrong here? Also, how can I verify this result with regard to expected FFT bin number (on a time based x-axis) and the magnitude value? Output in the natural order (option in FFT IP core) is something like this: I could not make anything of this result. Requesting your help. - Ram