RCB

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  1. Hey! Zybo Z7010 is a popular device with very good support here in the forum. I started with Zybo Z7020 over 7010 predominantly because of additional capabilities that I would like to be available for future projects. I have not faced any problems with the board because Digilent has the board support tools for z7020 and the hw/embedded programming experience is similar to the 7010. For hardware design, specific builds target specific boards. It will be very apparent if you are juggling between different boards with Vivado tool. Internal code might be good for building on different d
  2. Sorry, I missed email notification of your question. I have done something slightly similar to the fft implementation in http://web.mit.edu/6.111/www/f2015/projects/mitchgu_Project_Final_Report.pdf - they have documented it pretty well. I'm sure you can figure other details on the configuration - Xilinx documentation would be of good help too.
  3. Thank you for the thoughtful reply @zygot! _/\_ I'm really impressed with the idea of Tayloe detector for IQ demodulation when I learned it first. Your suggestion in a similar line of thought appears equally impressive. Thanks for the recommendation and for the push to keep looking for simpler answers! Yes, I will first try a small scale experiment with the Zybo I have - to get an idea on the resources required. I'll keep looking up for answers! Thank you so much!
  4. I'm carefully reviewing your comments. Thank you for the wonderful support. This is not a coursework oriented project but a personal one but still as a student. I am looking at resources that would contain details on interfacing external ADCs (zmod) - to analyze its complexity. RedPitaya board appears like an attractive choice too. " I can think of a few potential alternate ways to do this in the analog domain. Of course this depends on your measurement specifications. But it would simplify your signalling interface work and expense." - Can you share your suggestions on any daughter
  5. Input signals (2) are 5 MHz analog sinusoids - phase shifted. Project requires me to identify this phase difference between them + do some additional computations later. I am open to suggestions. Here are two main paths that I focused my search toward - 1) if there are daughter boards (RF, analog) that can do phase detection and give a digital output to read to the FPGA - would be ideal 2) if I need to interface high-sampling ADCs to sample the 5 MHz analog input and write phase detection logic on the FPGA - involved but I can try - most resources I looked online point FPGA for ph
  6. I am working towards a phase difference detection project to be developed on FPGA. I have Zybo Z7020 board. ADC sampling rate of 1 MSPS. My input signals are of frequency 5 MHz to 10 MHz. Zybo, unfortunately, is not equipped to sample such high frequency signals. I am unable to find external pmods or evaluation boards that can do phase detection (be it analog RF side or digital). Does anyone here have any suggestions for me to look up for? I'm also wondering if there could be any daughter boards that handle high frequency analog signals (ADC + mixers + filters (or) just ADCs) and hand ov
  7. Thanks @[email protected]! By AXI-stream signaling do you mean the handshaking signals between FFT and post-FFT processing blocks? (Problem with AXI stream register slice may be?) If it was a fixed offset I could account it for the latency in multipliers and CORDIC blocks but a fixed scaling factor is getting me all worried. For the former problem, I could try to add latency to the index signal magnitude_tuser so that both the index and magnitude_tdata have equal latency. I am now unsure about how to start debugging the scaling error. Any guidance would be of immense help! Grateful for your kind s
  8. Dear @[email protected], I would like to seek your comment on this question: Frequency for xfft aclk: 50 MHz (aclk is 50 MHz) In the below design I am trying to compute magnitude of FFT output (squaring through multiplier and square root using CORDIC). I am probing the signal bus magnitude_out which has the FFT magnitude data and tuser to index bin number corresponding to FFT output. Resolution of FFT is sampling rate/FFT_size: 961KSPS/4096 = 234.7 Hz However, I observe, from direct probing that every frequency component is scaled by 0.8. What I mean is, 100 KHz
  9. FFT IP: 4096 point, Fixed point, non-real time, unscaled Yes, you may populate the least significant bits with the DDS output. I tried square root operation for handling the FFT core output.
  10. Hey @petriggg I am still debugging some blocks and hence decided not to document with bugs.
  11. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling r
  12. Hi @[email protected] I think I got the design right after some experimentation. My mistake was about handling the real and imaginary components. Thank you for your suggestions. I'll document the steps and post it here hopefully soon. Appreciate your help. I would move on with replacing DDS synthesizer with XADC to test external signals with a function generator. - Ram
  13. Hi @[email protected] I still am facing issues with the design and request your help. I think the problem is with how the xfft core handles the input (32 bit) data. Some information on my input data: 1) Output of DDS compiler: 16 bit sine wave (DDS input 100 MHz clock, output: sine 100 KHz) 2) 16 bit o/p from DDS compiler is converted to signed magnitude form (dds_output - 1<<15) and is concatenated with 16'b0 (MSBs). Alternately, earlier I tried with DDS compiler output as is with 16'b0 concatenation. FFT details: 100 MHz clock, 4096, natural order, pipelined streaming
  14. @[email protected] I am sorry! The frequency is 50 kHz. My FFT resolution would be (100*10^6)/4096 about 24.5 kHz. X[3] would be the frequency bin with spike.