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Michal Hucik

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  1. Thank you for answer. I admit that I was a little carried away when I used my simple (misleading) test as a prerequisite for measuring performance. I underestimated a bit the number of operations that are associated with the measurement itself. I did a new a little more accurate measurement through the ILA. I measured the difference between the S_AXI_ARVALID and S_AXI_RVALID signal on the AXI slave. BRAM - 3 ticks (its nice, but this is not in my focus) DDR2 - 22 ticks = 220ns I'm probably wrong, but I'm based on the information in the Nexys A7 reference manual. Here is information about the transfer rate of 650Mbps at clk_period = 3077ps. So my assumption was that read_frq = 650Mbps / 32bit => (650*1024*1024)/32 => 21.2992 MHz => aprox 47ns (read access time for one 32bit word). Assumption according to the measured value of 220ns is 1 / 220ns => approx. 4.54 MHz => (1 / 220ns) * 32 => 138.7 Mbps
  2. I'm trying the neorv32 CPU on AXI4-lite bus. AXI_ACLK is 100MHz. I have connected BRAM memory block by AXI BRAM Controller and DDR2 memory interface by MIG. Input clock sys_clk_i connected to MIG is 200MHz. I wrote a simple test to measure the speed of reading: uint64_t start_time = neorv32_mtime_get_time ( ); uint32_t value = *(uint32_t*) addr; uint64_t end_time = neorv32_mtime_get_time ( ); When program is running from BRAM, so access time to BRAM is approx 70 ticks and to DDR2 120 ticks. When program is running from DDR2, so access time to BRAM is approx 995 ticks and to DDR2 1100 ticks. Why is there such a big difference and why is the program running from DDR2 so slow? The DDR2 memory is so saturated by random read access connections? Is it possible to activate some DDR2 cache that would speed it up? Or is DDR2 is not suitable to use by CPU instruction and data memory?
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