Vladimir

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Vladimir last won the day on October 1 2015

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  1. Hello James. Thank you for the last answer on my additional questions. I am completely satisfied with your answers and will continue my investigations from here. Thank you again for your help. I really moved ahead. Program started to work due to your main advice to use 2 commands, instead of one. I don't have other critical questions for now. Warm regards, Vladimir.
  2. Hello James. I would like to thank you very much for advises. It seems as it started to work. I even crossed my fingers. Although it works. In my code I have these lines: //first command1 to use internal voltage initial command1 = 32'b00001000000000000000000000000001; //in second command2 first 2 bits: 11 //next 4 bits: 1111 - to use all 8 outputs //next 12 bit are '1' - to produce full voltage. AD5628 uses 12 bits to define value voltage from the max voltage. //initial command2 = 32'b00000011111111111111111100000000; // max voltage – 2.5v //initial command2 = 32'b00000011111101111111111100000000; // half of max voltage – 1.25v initial command2 = 32'b00000011111100111111111100000000; // fourth of max voltage – 0.625v = ~ 0.63v First of all finally I saw an output voltage, initially max value = 2.5v. Secondary by changing value of command2 I saw different value of output voltage and that gave me more conformation that code is working. I am attaching my current code: Basys2_PmodDA4_code1.txt. Nevertheless I am not completely satisfied with code and I am going to experiment different things by changing the first version. I would like to ask you few questions: 1. I finished my code by bringing sync signal to high and parameter done = 1. Please advice – how better to let program know that it really completed? In this new for me world of digital programming it seems as method continues to work in infinitive loop. With done = 1 it goes inside of always @ (posedge clk) any way, but inside because of done = 1 it does nothing, avoiding part of code. Can it be improved? 2. Can we receive negative voltage here? If yes – how? 3. Of cause whole purpose of this exercise is to control the voltage as a function of time. So it should be some external method where we are watching the time and reload commands. Is that correct? Thanks, Vladimir Basys2_PmodDA4_code1.txt
  3. Hello James. Thank you very much for following my questions. According what you said - answer on my previous question is No. I don't need to send continuously 2 commands - but only once. I will try that approach now. I will change my code. I realized that I don't need to organize each command in code as I do. It will be easier to put each command as a parameter - constant and then to read each bit from that word at posedge of the clock. After first command will be sent, sync will go High for few periods, after Low and I will send second command. And it should be all. I think I will add button Go to perform that operation in one method and some logic to do that only once. This is my plan. It will take a some time, but I will certainly will let you know about my progress. Thanks, Vladimir.
  4. James, thanks a lot for your quick reply on my question. I understand what do you mean. Only I would like to clarify my task. I will describe to you my logic as I understand now. My program now sends the same 32 bit sequence to the PmodDA4 - the same and not correct sequence, because it combined two commands in one. Am I right if I say, that it should be sequence of 2 commands that will be repeated again and again: 32bit_command_for_using_internal_voltage, 32bit_command_for_using_all_outputs? I will try that for now, while waiting answer on my questions.
  5. Hello. I found similar question “Working with DA4 PMOD on Nexys 4” posted on 23 Oct. 2014 and answer from JColvin. I understand the hint about usage of internal voltage. Nevertheless I don’t see output voltages. It is not easy to me to follow applied code, because I have learned so far Verilog and example is given in VHDL. I am electrical engineer and programmer by education, but I am new to digital electronics and FPGAs. I have acquired some initial experience by learning book “Digital Design Using Digilent FPGA Boards. Verilog/ Active –HDL Edition” by Richard E.Haskell and Darrin M.Hanna from 2012. I have implemented many examples from the book on BASYS2 board that I have. Now I would like to see voltages on outputs of PmodDA4 that I connect to my BASYS2 board. For beginning I will be satisfied with direct (permanent) voltages. I have been trying few versions of code and didn’t succeed. Please, advise – what is wrong? May be many things… I will try to describe my logic in details and attach my code too. I use Verilog. I connect PmodDA4 to JA connector of BASYS2 board. I have to create 3 correct signals: SYNC, DIN and SCLK. According to documentation I assume that: 1. SYNC: JA1 (B2) – pio<72> in ucf file. 2. DIN: JA2 (A3) – pio<73> in ucf file. 3. SCLK: JA4 (B5) – pio<75> in ucf file. Default frequency of a board is 50 MHz. I use half of this frequency – 25 MHz as a SCLK signal. I understand logic of operation so: if SYNC is high – data from signal DIN does not go into internal register of PmodDA4. After SYNC went low – data starts to go into internal register of PmodDA4. It goes into PmodDA4 on each negedge of SCLK and it counted by PmodDA4. By data we mean signal DIN: 0 or 1. After transferring 32 bits into internal register of PmodDA4 we have to change SYNC on high. May be that not necessarily to do right away after 32 accumulated bits, but I do that in my code, because in any way we must bring SYNC high for min 15 ns and after low for initiation of a new cycle of writing data into internal register of PmodDA4. I control that process by variable count. I simulated the process with Aldec simulator and visually it seems to me correct. I assume that bit db31 on a page 7 of http://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf is a first bit in time among 32 bits that is clocked into internal register of PmodDA4. Here is a sequence of 32 bits that I try to produce, taking JColvin’s notice about using Internal source of power. Don’t care bits db31, 30, 29, 28: 0000. Command bits db27, 26, 25, 24: 1011. Address bits db23, 22, 21, 20: 1111 – command for having voltage on all 8 outputs. For AD5628 12 bits db19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8 equal to 1 for max output voltage: 111111111111. And last 8 bits db7, 6, 5, 4, 3, 2, 1, 0: 00000001. As I understood your notice bits db27 and db0 have to be 1 – for using internal voltage as a source. My code for the project is attached in file Basys2_PmodDA4_code.txt. Basys2_PmodDA4_code.txt
  6. Hello Josh. I am electrical engineer and programmer by education, but I am new to digital electronics and FPGAs. I have acquired some initial experience by learning book “Digital Design Using Digilent FPGA Boards. Verilog/ Active –HDL Edition” by Richard E.Haskell and Darrin M.Hanna from 2012. I have implemented many examples from the book on BASYS2 board that I have. Now I would like to see voltages on outputs of PmodDA4 that I connect to my BASYS2 board. For beginning I will be satisfied with direct (permanent) voltages. I have been trying few versions of code and didn’t succeed. Please, advise – what is wrong? May be many things… I will try to describe you my logic in details and will send my code too. I use Verilog. I connect PmodDA4 to JA connector of BASYS2 board. I have to create 3 correct signals: SYNC, DIN and SCLK. According to documentation I assume that 1. SYNC: JA1 (B2) – pio<72> in ucf file. 2. DIN: JA2 (A3) – pio<73> in ucf file. 3. SCLK: JA4 (B5) – pio<75> in ucf file. Default frequency of a board is 50 MHz. I use half of this frequency – 25 MHz as a SCLK signal. I understand logic of operation so: if SYNC is high – data from signal DIN does not go into internal register of PmodDA4. After SYNC went low – data starts to go into internal register of PmodDA4. It goes into PmodDA4 on each negedge of SCLK and it counted by PmodDA4. By data we mean signal DIN: 0 or 1. After transferring 32 bits into internal register of PmodDA4 we have to change SYNC on high. May be that not necessarily to do right away after 32 accumulated bits, but I do that in my code, because in any way we must bring SYNC high for min 15 ns and after low for initiation of a new cycle of writing data into internal register of PmodDA4. I control that process by variable count. I simulated the process with Aldec simulator and visually it seems to me correct. I assume that bit db31 on a page 7 of http://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf is a first bit in time among 32 bits that is clocked into internal register of PmodDA4. Here is a sequence of 32 bits that I try to produce, taking your notice about using Internal source of power. Don’t care bits db31, 30, 29, 28: 0000. Command bits db27, 26, 25, 24: 1011. Address bits db23, 22, 21, 20: 1111 – command for having voltage on all 8 outputs. For AD5628 12 bits db19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8 equal to 1 for max output voltage: 111111111111. And last 8 bits db7, 6, 5, 4, 3, 2, 1, 0: 00000001. As I understood your notice bits db27 and db0 have to be 1 – for using internal voltage as a source. Kind regards, Vladimir Basys2_PmodDA4_code.txt