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  1. JColvin. Thank you for the replay! Bad wording on my part. I can set the alarm, set the time, but the clock stays at 00:00 which is why I suspected the clock. Other example programs work with the clock so I know it is physically connected to the FPGA. I am combining two example 'alarm clocks' .. one whose output is in binary and the second a binary to 7-segment converter .. so I have obviously made a coding error. The examples I am using are in verilog, so I well stick with that for now. Learning a new programming language (and hardware!) is always interesting! Jim
  2. I am using the Basys3 board, Vicado 2019.1, and verilog as a "new learner" in an attempt to implement an alarm clock found on the web. I am unclear as to how to set up the clock in the xdc file My source module file... module aclock ( input clock_100Mhz,// 100 Mhz clock source on Basys 3 FPGA input reset, // sw0 Active high reset pulse, to set the time to the input hour and minute. // (as defined by the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00. // It should also set the alarm value to 0.00.00, and to set the