Wyllyam

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About Wyllyam

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  1. jchisum, You're correct. I fixed the typo in the tutorial. Thank you for the feedback! Were you able to recreate the project when typing the name with underscores? -Will
  2. @kb5pgy, There's definitely a lot of information packed into this webinar. I'm sorry to hear it was frustrating and you weren't able to get the value out of it that you hoped. For future webinars, we will work towards more clearly articulating the experience level needed, and to improve the educational quality of the content itself. With this webinar in particular, we say no FPGA experience is required because the webinar goes step-by-step. However, it can still be challenging, especially with condensing so much information into a few hours. I hope that you were still able to get something out of it. You can find a recording at the original landing page where you registered for the event.(FYI @dry, to answer your original question). With this recording you can pause and back up as needed, and hopefully that will help you resolve some of your questions that we weren't able to answer during the webinar itself.
  3. @zygot, Your feedback is appreciated. I grabbed an Eclypse Z7 from our stock and am thoroughly working through all of our provided materials and demos. After working through this, I will: Provide feedback to R&D, combined with the points you brought up, so we can work towards improving the user experience Fill any gaps in our getting started materials to ensure easy adoption Revise, as necessary, our product descriptions to make sure the product meets expectations
  4. Zygot, I poked around my installation of 2019.2, which was a WebPACK installation, but I don't think there's a away to see that explicitly after the fact. Though, you could maybe take a roundabout way of checking your licenses with Xilinx. This wouldn't guarantee it was/wasn't a WebPACK install, but you may be able to make a reasonable assumption from there. Just a thought. Back to the main topic at hand: The XCZU3EG is supported by WebPACK, as is the XCZU5EV. "Starting 2019.2, Xilinx SDSoC™ development environments are unified into an all-in-one Vitis™ unified software platform. There will be no 2019.2 or future releases of Xilinx SDSoc Development Environment." (link) This does not include MIPI CSI-2 IP, so we provided a voucher for this with the Genesys ZU board because we thought it would be valuable for vision applications for which the Genesys ZU is well-suited. I hope that clears this up some more, but let me know if you have other thoughts or questions.