rddlr

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  1. I fixed this issue but nothing changes. Do you mind if it could be a timing problem? If i delete "and i_clk ='1'" from the io_test process the design meet timings. Can you help me to understand why?
  2. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store