jason.s

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  1. Hi Ana-Maria, The spi_ss_i signal should also be updated to F16 in your board file for the two boards. https://github.com/Digilent/vivado-boards/blob/master/new/board_files/arty-z7-20/A.0/part0_pins.xml Thanks, Jason
  2. I am trying to build the Z7-20 base linux project found here: https://github.com/Digilent/Arty-Z7-20-base-linux https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty_z7_sch.pdf What I found is the project fails to build due to two signals being constrained to the same pin T16. One signal is shield_dp0_dp13_tri_io[10]. The other is shield_SPI_ss_io. After looking at the schematics, it seems the IO10 signal should be connected to T16 which goes to the shield header, and the SPI_ss signal should be connected to F16 which goes to the SPI header. Is this correct? Looking at the history of the constraints, the ss signal has been incorrectly on T16 since the start of the project. Without making the change, the project fails to build. I don't understand how I could be the first person to try to build the project.